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IEICE TRANSACTIONS on Fundamentals

Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature

Takahiro NAKAYAMA, Masanori HASHIMOTO

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Summary :

VLSIs that perform signal processing near infrared sensors cooled to ultra-low temperature are demanded. Delay test of those chips must be executed at ultra-low temperature while functional test could be performed at room temperature as long as hold timing errors do not occur. In this letter, we focus on the hold timing violation and evaluate the feasibility of functional test of ultra-low temperature circuits at room temperature. Experimental evaluation with a case study shows that the functional test at room temperature is possible.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E102-A No.7 pp.914-917
Publication Date
2019/07/01
Publicized
Online ISSN
1745-1337
DOI
10.1587/transfun.E102.A.914
Type of Manuscript
Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category

Authors

Takahiro NAKAYAMA
  Osaka University
Masanori HASHIMOTO
  Osaka University

Keyword