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In this paper, a new heuristic algorithm is proposed to optimize the power domain clustering in controlling-value-based (CV-based) power gating technology. In this algorithm, both the switching activity of sleep signals (*p*) and the overall numbers of sleep gates (gate count, *N*) are considered, and the sum of the product of *p* and *N* is optimized. The algorithm effectively exerts the total power reduction obtained from the CV-based power gating. Even when the maximum depth is kept to be the same, the proposed algorithm can still achieve power reduction approximately 10% more than that of the prior algorithms. Furthermore, detailed comparison between the proposed heuristic algorithm and other possible heuristic algorithms are also presented. HSPICE simulation results show that over 26% of total power reduction can be obtained by using the new heuristic algorithm. In addition, the effect of dynamic power reduction through the CV-based power gating method and the delay overhead caused by the switching of sleep transistors are also shown in this paper.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E92-A No.12 pp.3111-3118

- Publication Date
- 2009/12/01

- Publicized

- Online ISSN
- 1745-1337

- DOI
- 10.1587/transfun.E92.A.3111

- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

- Category
- Logic Synthesis, Test and Verfication

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Lei CHEN, Shinji KIMURA, "Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity" in IEICE TRANSACTIONS on Fundamentals,
vol. E92-A, no. 12, pp. 3111-3118, December 2009, doi: 10.1587/transfun.E92.A.3111.

Abstract: In this paper, a new heuristic algorithm is proposed to optimize the power domain clustering in controlling-value-based (CV-based) power gating technology. In this algorithm, both the switching activity of sleep signals (*p*) and the overall numbers of sleep gates (gate count, *N*) are considered, and the sum of the product of *p* and *N* is optimized. The algorithm effectively exerts the total power reduction obtained from the CV-based power gating. Even when the maximum depth is kept to be the same, the proposed algorithm can still achieve power reduction approximately 10% more than that of the prior algorithms. Furthermore, detailed comparison between the proposed heuristic algorithm and other possible heuristic algorithms are also presented. HSPICE simulation results show that over 26% of total power reduction can be obtained by using the new heuristic algorithm. In addition, the effect of dynamic power reduction through the CV-based power gating method and the delay overhead caused by the switching of sleep transistors are also shown in this paper.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E92.A.3111/_p

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@ARTICLE{e92-a_12_3111,

author={Lei CHEN, Shinji KIMURA, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity},

year={2009},

volume={E92-A},

number={12},

pages={3111-3118},

abstract={In this paper, a new heuristic algorithm is proposed to optimize the power domain clustering in controlling-value-based (CV-based) power gating technology. In this algorithm, both the switching activity of sleep signals (*p*) and the overall numbers of sleep gates (gate count, *N*) are considered, and the sum of the product of *p* and *N* is optimized. The algorithm effectively exerts the total power reduction obtained from the CV-based power gating. Even when the maximum depth is kept to be the same, the proposed algorithm can still achieve power reduction approximately 10% more than that of the prior algorithms. Furthermore, detailed comparison between the proposed heuristic algorithm and other possible heuristic algorithms are also presented. HSPICE simulation results show that over 26% of total power reduction can be obtained by using the new heuristic algorithm. In addition, the effect of dynamic power reduction through the CV-based power gating method and the delay overhead caused by the switching of sleep transistors are also shown in this paper.},

keywords={},

doi={10.1587/transfun.E92.A.3111},

ISSN={1745-1337},

month={December},}

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TY - JOUR

TI - Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 3111

EP - 3118

AU - Lei CHEN

AU - Shinji KIMURA

PY - 2009

DO - 10.1587/transfun.E92.A.3111

JO - IEICE TRANSACTIONS on Fundamentals

SN - 1745-1337

VL - E92-A

IS - 12

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - December 2009

AB - In this paper, a new heuristic algorithm is proposed to optimize the power domain clustering in controlling-value-based (CV-based) power gating technology. In this algorithm, both the switching activity of sleep signals (*p*) and the overall numbers of sleep gates (gate count, *N*) are considered, and the sum of the product of *p* and *N* is optimized. The algorithm effectively exerts the total power reduction obtained from the CV-based power gating. Even when the maximum depth is kept to be the same, the proposed algorithm can still achieve power reduction approximately 10% more than that of the prior algorithms. Furthermore, detailed comparison between the proposed heuristic algorithm and other possible heuristic algorithms are also presented. HSPICE simulation results show that over 26% of total power reduction can be obtained by using the new heuristic algorithm. In addition, the effect of dynamic power reduction through the CV-based power gating method and the delay overhead caused by the switching of sleep transistors are also shown in this paper.

ER -