IEICE TRANSACTIONS on Fundamentals
On Clock-Based Fault Analysis Attack for an AES Hardware Using RSL
Summary :
As one of the logic-level countermeasures against DPA (Differential Power Analysis) attacks, Random Switching Logic (RSL) was proposed by Suzuki, Saeki and Ichikawa in 2004 . The RSL technique was applied to AES hardware and a prototype chip was implement with a 0.13-µm standard CMOS library for evaluating the DPA resistance . Although the main purpose of using RSL is to resist the DPA attacks, our experimental results of Clock-based Fault Analysis (CFA) show that one can reveal the secret information from the prototype chip. This paper explains the mechanism of the CFA attack and discusses the reason for the success of the attack against a prototype implementation of AES with RSL (RSL-AES). Furthermore, we consider an ideal RSL-AES implementation that counteracts the CFA attacks.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.1 pp.172-179
- Publication Date
- 2010/01/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.172
- Type of Manuscript
- Special Section PAPER (Special Section on Cryptography and Information Security)
- Category
- Cryptanalysis
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Kazuo SAKIYAMA, Kazuo OHTA, "On Clock-Based Fault Analysis Attack for an AES Hardware Using RSL" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 1, pp. 172-179, January 2010, doi: 10.1587/transfun.E93.A.172.
Abstract: As one of the logic-level countermeasures against DPA (Differential Power Analysis) attacks, Random Switching Logic (RSL) was proposed by Suzuki, Saeki and Ichikawa in 2004 . The RSL technique was applied to AES hardware and a prototype chip was implement with a 0.13-µm standard CMOS library for evaluating the DPA resistance . Although the main purpose of using RSL is to resist the DPA attacks, our experimental results of Clock-based Fault Analysis (CFA) show that one can reveal the secret information from the prototype chip. This paper explains the mechanism of the CFA attack and discusses the reason for the success of the attack against a prototype implementation of AES with RSL (RSL-AES). Furthermore, we consider an ideal RSL-AES implementation that counteracts the CFA attacks.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.172/_p
Copy
@ARTICLE{e93-a_1_172,
author={Kazuo SAKIYAMA, Kazuo OHTA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={On Clock-Based Fault Analysis Attack for an AES Hardware Using RSL},
year={2010},
volume={E93-A},
number={1},
pages={172-179},
abstract={As one of the logic-level countermeasures against DPA (Differential Power Analysis) attacks, Random Switching Logic (RSL) was proposed by Suzuki, Saeki and Ichikawa in 2004 . The RSL technique was applied to AES hardware and a prototype chip was implement with a 0.13-µm standard CMOS library for evaluating the DPA resistance . Although the main purpose of using RSL is to resist the DPA attacks, our experimental results of Clock-based Fault Analysis (CFA) show that one can reveal the secret information from the prototype chip. This paper explains the mechanism of the CFA attack and discusses the reason for the success of the attack against a prototype implementation of AES with RSL (RSL-AES). Furthermore, we consider an ideal RSL-AES implementation that counteracts the CFA attacks.},
keywords={},
doi={10.1587/transfun.E93.A.172},
ISSN={1745-1337},
month={January},}
Copy
TY - JOUR
TI - On Clock-Based Fault Analysis Attack for an AES Hardware Using RSL
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 172
EP - 179
AU - Kazuo SAKIYAMA
AU - Kazuo OHTA
PY - 2010
DO - 10.1587/transfun.E93.A.172
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2010
AB - As one of the logic-level countermeasures against DPA (Differential Power Analysis) attacks, Random Switching Logic (RSL) was proposed by Suzuki, Saeki and Ichikawa in 2004 . The RSL technique was applied to AES hardware and a prototype chip was implement with a 0.13-µm standard CMOS library for evaluating the DPA resistance . Although the main purpose of using RSL is to resist the DPA attacks, our experimental results of Clock-based Fault Analysis (CFA) show that one can reveal the secret information from the prototype chip. This paper explains the mechanism of the CFA attack and discusses the reason for the success of the attack against a prototype implementation of AES with RSL (RSL-AES). Furthermore, we consider an ideal RSL-AES implementation that counteracts the CFA attacks.
ER -
English
