IEICE TRANSACTIONS on Fundamentals
Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
Summary :
Clock gating is the insertion of control signal for registers to switch off unnecessary clock signals selectively without violating the functional correctness of the original design so as to reduce the dynamic power consumption. Commercial EDA tools usually have a mechanism to generate clock gating logic based on the structural method where the control signals specified by designers are used, and the effectiveness of the clock gating depends on the specified control signals. In the research, we focus on the automatic clock gating logic generation and propose a method based on the candidate extraction and control signal selection. We formalize the control signal selection using linear formulae and devise an optimization method based on BDD. The method is effective for circuits with a lot of shared candidates by different registers. The method is applied to counter circuits to check the co-relation with power simulation results and a set of benchmark circuits. 19.1-71.9% power reduction has been found on counter circuitsafter layout and 2.3-18.0% cost reduction on benchmark circuits.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.12 pp.2472-2480
- Publication Date
- 2010/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.2472
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis, Test and Verification
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Keyword
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Xin MAN, Takashi HORIYAMA, Shinji KIMURA, "Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2472-2480, December 2010, doi: 10.1587/transfun.E93.A.2472.
Abstract: Clock gating is the insertion of control signal for registers to switch off unnecessary clock signals selectively without violating the functional correctness of the original design so as to reduce the dynamic power consumption. Commercial EDA tools usually have a mechanism to generate clock gating logic based on the structural method where the control signals specified by designers are used, and the effectiveness of the clock gating depends on the specified control signals. In the research, we focus on the automatic clock gating logic generation and propose a method based on the candidate extraction and control signal selection. We formalize the control signal selection using linear formulae and devise an optimization method based on BDD. The method is effective for circuits with a lot of shared candidates by different registers. The method is applied to counter circuits to check the co-relation with power simulation results and a set of benchmark circuits. 19.1-71.9% power reduction has been found on counter circuitsafter layout and 2.3-18.0% cost reduction on benchmark circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2472/_p
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@ARTICLE{e93-a_12_2472,
author={Xin MAN, Takashi HORIYAMA, Shinji KIMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating},
year={2010},
volume={E93-A},
number={12},
pages={2472-2480},
abstract={Clock gating is the insertion of control signal for registers to switch off unnecessary clock signals selectively without violating the functional correctness of the original design so as to reduce the dynamic power consumption. Commercial EDA tools usually have a mechanism to generate clock gating logic based on the structural method where the control signals specified by designers are used, and the effectiveness of the clock gating depends on the specified control signals. In the research, we focus on the automatic clock gating logic generation and propose a method based on the candidate extraction and control signal selection. We formalize the control signal selection using linear formulae and devise an optimization method based on BDD. The method is effective for circuits with a lot of shared candidates by different registers. The method is applied to counter circuits to check the co-relation with power simulation results and a set of benchmark circuits. 19.1-71.9% power reduction has been found on counter circuitsafter layout and 2.3-18.0% cost reduction on benchmark circuits.},
keywords={},
doi={10.1587/transfun.E93.A.2472},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2472
EP - 2480
AU - Xin MAN
AU - Takashi HORIYAMA
AU - Shinji KIMURA
PY - 2010
DO - 10.1587/transfun.E93.A.2472
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - Clock gating is the insertion of control signal for registers to switch off unnecessary clock signals selectively without violating the functional correctness of the original design so as to reduce the dynamic power consumption. Commercial EDA tools usually have a mechanism to generate clock gating logic based on the structural method where the control signals specified by designers are used, and the effectiveness of the clock gating depends on the specified control signals. In the research, we focus on the automatic clock gating logic generation and propose a method based on the candidate extraction and control signal selection. We formalize the control signal selection using linear formulae and devise an optimization method based on BDD. The method is effective for circuits with a lot of shared candidates by different registers. The method is applied to counter circuits to check the co-relation with power simulation results and a set of benchmark circuits. 19.1-71.9% power reduction has been found on counter circuitsafter layout and 2.3-18.0% cost reduction on benchmark circuits.
ER -
English
