Variation-Aware Task and Communication Scheduling in MPSoCs for Power-Yield Maximization
Summary :
Parameter variations reveal themselves as different frequency and leakage powers per instances of the same MPSoC. By the increasing variation with technology scaling, worst-case-based scheduling algorithms result in either increasingly less optimal schedules or otherwise more lost yield. To address this problem, this paper introduces a variation-aware task and communication scheduling algorithm for multiprocessor system-on-chip (MPSoC). We consider both delay and leakage power variations during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power. Our algorithm takes advantage of event tables to accelerate the statistical timing and power analysis. We use genetic algorithm to find the best schedule that maximizes power-yield under a performance-yield constraint. Experimental results on real world benchmarks show that our proposed algorithm achieves 16.6% power-yield improvement on average over deterministic worst-case-based scheduling.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.12 pp.2542-2550
- Publication Date
- 2010/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.2542
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- High-Level Synthesis and System-Level Design
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Mahmoud MOMTAZPOUR, Maziar GOUDARZI, Esmaeil SANAEI, "Variation-Aware Task and Communication Scheduling in MPSoCs for Power-Yield Maximization" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 12, pp. 2542-2550, December 2010, doi: 10.1587/transfun.E93.A.2542.
Abstract: Parameter variations reveal themselves as different frequency and leakage powers per instances of the same MPSoC. By the increasing variation with technology scaling, worst-case-based scheduling algorithms result in either increasingly less optimal schedules or otherwise more lost yield. To address this problem, this paper introduces a variation-aware task and communication scheduling algorithm for multiprocessor system-on-chip (MPSoC). We consider both delay and leakage power variations during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power. Our algorithm takes advantage of event tables to accelerate the statistical timing and power analysis. We use genetic algorithm to find the best schedule that maximizes power-yield under a performance-yield constraint. Experimental results on real world benchmarks show that our proposed algorithm achieves 16.6% power-yield improvement on average over deterministic worst-case-based scheduling.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.2542/_p
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@ARTICLE{e93-a_12_2542,
author={Mahmoud MOMTAZPOUR, Maziar GOUDARZI, Esmaeil SANAEI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Variation-Aware Task and Communication Scheduling in MPSoCs for Power-Yield Maximization},
year={2010},
volume={E93-A},
number={12},
pages={2542-2550},
abstract={Parameter variations reveal themselves as different frequency and leakage powers per instances of the same MPSoC. By the increasing variation with technology scaling, worst-case-based scheduling algorithms result in either increasingly less optimal schedules or otherwise more lost yield. To address this problem, this paper introduces a variation-aware task and communication scheduling algorithm for multiprocessor system-on-chip (MPSoC). We consider both delay and leakage power variations during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power. Our algorithm takes advantage of event tables to accelerate the statistical timing and power analysis. We use genetic algorithm to find the best schedule that maximizes power-yield under a performance-yield constraint. Experimental results on real world benchmarks show that our proposed algorithm achieves 16.6% power-yield improvement on average over deterministic worst-case-based scheduling.},
keywords={},
doi={10.1587/transfun.E93.A.2542},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Variation-Aware Task and Communication Scheduling in MPSoCs for Power-Yield Maximization
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2542
EP - 2550
AU - Mahmoud MOMTAZPOUR
AU - Maziar GOUDARZI
AU - Esmaeil SANAEI
PY - 2010
DO - 10.1587/transfun.E93.A.2542
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2010
AB - Parameter variations reveal themselves as different frequency and leakage powers per instances of the same MPSoC. By the increasing variation with technology scaling, worst-case-based scheduling algorithms result in either increasingly less optimal schedules or otherwise more lost yield. To address this problem, this paper introduces a variation-aware task and communication scheduling algorithm for multiprocessor system-on-chip (MPSoC). We consider both delay and leakage power variations during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power. Our algorithm takes advantage of event tables to accelerate the statistical timing and power analysis. We use genetic algorithm to find the best schedule that maximizes power-yield under a performance-yield constraint. Experimental results on real world benchmarks show that our proposed algorithm achieves 16.6% power-yield improvement on average over deterministic worst-case-based scheduling.
ER -
English
