IEICE TRANSACTIONS on Fundamentals
Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism
Summary :
A novel method to efficiently synthesize hardware from a large behavioral description in behavioral synthesis is proposed. For a program with functions executable in parallel, this proposed method determines a behavioral partitioning which simultaneously minimizes the overall datapath area and the complexity of the controller while maximizing performance of a synthesized circuit by fully exploiting function-level parallelism of a behavioral description. This method is formulated as an integer programming problem. Experimental results demonstrate that this method leads to a shift of the explorable design space so that superior solutions which could not be explored by earlier work are included, showing the effectiveness of our proposed method.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.2 pp.488-499
- Publication Date
- 2010/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.488
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Yuko HARA, Hiroyuki TOMIYAMA, Shinya HONDA, Hiroaki TAKADA, "Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 2, pp. 488-499, February 2010, doi: 10.1587/transfun.E93.A.488.
Abstract: A novel method to efficiently synthesize hardware from a large behavioral description in behavioral synthesis is proposed. For a program with functions executable in parallel, this proposed method determines a behavioral partitioning which simultaneously minimizes the overall datapath area and the complexity of the controller while maximizing performance of a synthesized circuit by fully exploiting function-level parallelism of a behavioral description. This method is formulated as an integer programming problem. Experimental results demonstrate that this method leads to a shift of the explorable design space so that superior solutions which could not be explored by earlier work are included, showing the effectiveness of our proposed method.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.488/_p
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@ARTICLE{e93-a_2_488,
author={Yuko HARA, Hiroyuki TOMIYAMA, Shinya HONDA, Hiroaki TAKADA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism},
year={2010},
volume={E93-A},
number={2},
pages={488-499},
abstract={A novel method to efficiently synthesize hardware from a large behavioral description in behavioral synthesis is proposed. For a program with functions executable in parallel, this proposed method determines a behavioral partitioning which simultaneously minimizes the overall datapath area and the complexity of the controller while maximizing performance of a synthesized circuit by fully exploiting function-level parallelism of a behavioral description. This method is formulated as an integer programming problem. Experimental results demonstrate that this method leads to a shift of the explorable design space so that superior solutions which could not be explored by earlier work are included, showing the effectiveness of our proposed method.},
keywords={},
doi={10.1587/transfun.E93.A.488},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 488
EP - 499
AU - Yuko HARA
AU - Hiroyuki TOMIYAMA
AU - Shinya HONDA
AU - Hiroaki TAKADA
PY - 2010
DO - 10.1587/transfun.E93.A.488
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2010
AB - A novel method to efficiently synthesize hardware from a large behavioral description in behavioral synthesis is proposed. For a program with functions executable in parallel, this proposed method determines a behavioral partitioning which simultaneously minimizes the overall datapath area and the complexity of the controller while maximizing performance of a synthesized circuit by fully exploiting function-level parallelism of a behavioral description. This method is formulated as an integer programming problem. Experimental results demonstrate that this method leads to a shift of the explorable design space so that superior solutions which could not be explored by earlier work are included, showing the effectiveness of our proposed method.
ER -
English
