SystemVerilog-Based Verification Environment Employing Multiple Inheritance of SystemC
Summary :
In this paper, we describe a verification environment which is based on a constrained random layered testbench using SystemVerilog OOP. As SystemVerilog OOP technique does not allow multiple inheritance, we adopt SystemC to design components of a verification environment which employ multiple inheritance. Then SystemC design unit is linked to a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes the design phase of verification environment simple and easy through source code reusability without corruption due to multi-level single inheritance.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.5 pp.989-992
- Publication Date
- 2010/05/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.989
- Type of Manuscript
- LETTER
- Category
- VLSI Design Technology and CAD
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Keyword
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Myoung-Keun YOU, Gi-Yong SONG, "SystemVerilog-Based Verification Environment Employing Multiple Inheritance of SystemC" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 5, pp. 989-992, May 2010, doi: 10.1587/transfun.E93.A.989.
Abstract: In this paper, we describe a verification environment which is based on a constrained random layered testbench using SystemVerilog OOP. As SystemVerilog OOP technique does not allow multiple inheritance, we adopt SystemC to design components of a verification environment which employ multiple inheritance. Then SystemC design unit is linked to a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes the design phase of verification environment simple and easy through source code reusability without corruption due to multi-level single inheritance.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.989/_p
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@ARTICLE{e93-a_5_989,
author={Myoung-Keun YOU, Gi-Yong SONG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={SystemVerilog-Based Verification Environment Employing Multiple Inheritance of SystemC},
year={2010},
volume={E93-A},
number={5},
pages={989-992},
abstract={In this paper, we describe a verification environment which is based on a constrained random layered testbench using SystemVerilog OOP. As SystemVerilog OOP technique does not allow multiple inheritance, we adopt SystemC to design components of a verification environment which employ multiple inheritance. Then SystemC design unit is linked to a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes the design phase of verification environment simple and easy through source code reusability without corruption due to multi-level single inheritance.},
keywords={},
doi={10.1587/transfun.E93.A.989},
ISSN={1745-1337},
month={May},}
Copy
TY - JOUR
TI - SystemVerilog-Based Verification Environment Employing Multiple Inheritance of SystemC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 989
EP - 992
AU - Myoung-Keun YOU
AU - Gi-Yong SONG
PY - 2010
DO - 10.1587/transfun.E93.A.989
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2010
AB - In this paper, we describe a verification environment which is based on a constrained random layered testbench using SystemVerilog OOP. As SystemVerilog OOP technique does not allow multiple inheritance, we adopt SystemC to design components of a verification environment which employ multiple inheritance. Then SystemC design unit is linked to a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes the design phase of verification environment simple and easy through source code reusability without corruption due to multi-level single inheritance.
ER -
English
