IEICE TRANSACTIONS on Fundamentals
High-Speed FPGA Implementation of the SHA-1 Hash Function
Summary :
This paper presents a high-speed SHA-1 implementation. Unlike the conventional unfolding transformation, the proposed unfolding transformation technique makes the combined hash operation blocks to have almost the same delay overhead regardless of the unfolding factor. It can achieve high throughput of SHA-1 implementation by avoiding the performance degradation caused by the first hash computation. We demonstrate the proposed SHA-1 architecture on a FPGA chip. From the experimental results, the SHA-1 architecture with unfolding factor 5 shows 1.17 Gbps. The proposed SHA-1 architecture can achieve about 31% performance improvements compared to its counterparts. Thus, the proposed SHA-1 can be applicable for the security of the high-speed but compact mobile appliances.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.9 pp.1873-1876
- Publication Date
- 2011/09/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E94.A.1873
- Type of Manuscript
- LETTER
- Category
- Cryptography and Information Security
Authors
Keyword
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Je-Hoon LEE, Sang-Choon KIM, Young-Jun SONG, "High-Speed FPGA Implementation of the SHA-1 Hash Function" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 9, pp. 1873-1876, September 2011, doi: 10.1587/transfun.E94.A.1873.
Abstract: This paper presents a high-speed SHA-1 implementation. Unlike the conventional unfolding transformation, the proposed unfolding transformation technique makes the combined hash operation blocks to have almost the same delay overhead regardless of the unfolding factor. It can achieve high throughput of SHA-1 implementation by avoiding the performance degradation caused by the first hash computation. We demonstrate the proposed SHA-1 architecture on a FPGA chip. From the experimental results, the SHA-1 architecture with unfolding factor 5 shows 1.17 Gbps. The proposed SHA-1 architecture can achieve about 31% performance improvements compared to its counterparts. Thus, the proposed SHA-1 can be applicable for the security of the high-speed but compact mobile appliances.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.1873/_p
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@ARTICLE{e94-a_9_1873,
author={Je-Hoon LEE, Sang-Choon KIM, Young-Jun SONG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Speed FPGA Implementation of the SHA-1 Hash Function},
year={2011},
volume={E94-A},
number={9},
pages={1873-1876},
abstract={This paper presents a high-speed SHA-1 implementation. Unlike the conventional unfolding transformation, the proposed unfolding transformation technique makes the combined hash operation blocks to have almost the same delay overhead regardless of the unfolding factor. It can achieve high throughput of SHA-1 implementation by avoiding the performance degradation caused by the first hash computation. We demonstrate the proposed SHA-1 architecture on a FPGA chip. From the experimental results, the SHA-1 architecture with unfolding factor 5 shows 1.17 Gbps. The proposed SHA-1 architecture can achieve about 31% performance improvements compared to its counterparts. Thus, the proposed SHA-1 can be applicable for the security of the high-speed but compact mobile appliances.},
keywords={},
doi={10.1587/transfun.E94.A.1873},
ISSN={1745-1337},
month={September},}
Copy
TY - JOUR
TI - High-Speed FPGA Implementation of the SHA-1 Hash Function
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1873
EP - 1876
AU - Je-Hoon LEE
AU - Sang-Choon KIM
AU - Young-Jun SONG
PY - 2011
DO - 10.1587/transfun.E94.A.1873
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2011
AB - This paper presents a high-speed SHA-1 implementation. Unlike the conventional unfolding transformation, the proposed unfolding transformation technique makes the combined hash operation blocks to have almost the same delay overhead regardless of the unfolding factor. It can achieve high throughput of SHA-1 implementation by avoiding the performance degradation caused by the first hash computation. We demonstrate the proposed SHA-1 architecture on a FPGA chip. From the experimental results, the SHA-1 architecture with unfolding factor 5 shows 1.17 Gbps. The proposed SHA-1 architecture can achieve about 31% performance improvements compared to its counterparts. Thus, the proposed SHA-1 can be applicable for the security of the high-speed but compact mobile appliances.
ER -
English
