High-Performance Architecture for Concurrent Error Detection for AES Processors

Takeshi SUGAWARA; Naofumi HOMMA; Takafumi AOKI; Akashi SATOH

doi:10.1587/transfun.E94.A.1971

High-Performance Architecture for Concurrent Error Detection for AES Processors

Takeshi SUGAWARA, Naofumi HOMMA, Takafumi AOKI, Akashi SATOH

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This paper proposes an efficient scheme for concurrent error detection for hardware implementations of the block cipher AES. In the proposed scheme, the circuit component for the round function is divided into two stages, which are used alternately for encryption (or decryption) and error checking in a pipeline. The proposed scheme has a limited overhead with respect to size and speed for the following reasons. Firstly, the need for a double number of clock cycles is eliminated by virtue of the reduced critical path. Secondly, the scheme only requires minimal additional circuitry for error detection since the detection is performed by the remaining encryption (or decryption) components within the pipeline. AES hardware with the proposed scheme was designed and synthesized by using 90-nm CMOS standard cell library with various constraints. As a result, the proposed circuit achieved 1.66 Gbps @ 12.9 Kgates for the compact version and 4.22 Gbps @ 30.7 Kgates for the high-speed version. These performance characteristics are comparable to those of a basic AES circuit without error detection, where the overhead of the proposed scheme is estimated to be 14.5% at maximum. The proposed circuit was fabricated in the form of a chip, and its error detection performance was evaluated through experiments. The chip was tested with respect to fault injection by using clock glitch, and the proposed scheme successfully detected and reacted to all introduced errors.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.10 pp.1971-1980

Publication Date: 2011/10/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E94.A.1971

Type of Manuscript: PAPER

Category: Cryptography and Information Security

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Takeshi SUGAWARA, Naofumi HOMMA, Takafumi AOKI, Akashi SATOH, "High-Performance Architecture for Concurrent Error Detection for AES Processors" in IEICE TRANSACTIONS on Fundamentals, vol. E94-A, no. 10, pp. 1971-1980, October 2011, doi: 10.1587/transfun.E94.A.1971.
Abstract: This paper proposes an efficient scheme for concurrent error detection for hardware implementations of the block cipher AES. In the proposed scheme, the circuit component for the round function is divided into two stages, which are used alternately for encryption (or decryption) and error checking in a pipeline. The proposed scheme has a limited overhead with respect to size and speed for the following reasons. Firstly, the need for a double number of clock cycles is eliminated by virtue of the reduced critical path. Secondly, the scheme only requires minimal additional circuitry for error detection since the detection is performed by the remaining encryption (or decryption) components within the pipeline. AES hardware with the proposed scheme was designed and synthesized by using 90-nm CMOS standard cell library with various constraints. As a result, the proposed circuit achieved 1.66 Gbps @ 12.9 Kgates for the compact version and 4.22 Gbps @ 30.7 Kgates for the high-speed version. These performance characteristics are comparable to those of a basic AES circuit without error detection, where the overhead of the proposed scheme is estimated to be 14.5% at maximum. The proposed circuit was fabricated in the form of a chip, and its error detection performance was evaluated through experiments. The chip was tested with respect to fault injection by using clock glitch, and the proposed scheme successfully detected and reacted to all introduced errors.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.1971/_p

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@ARTICLE{e94-a_10_1971,
author={Takeshi SUGAWARA, Naofumi HOMMA, Takafumi AOKI, Akashi SATOH, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Performance Architecture for Concurrent Error Detection for AES Processors},
year={2011},
volume={E94-A},
number={10},
pages={1971-1980},
abstract={This paper proposes an efficient scheme for concurrent error detection for hardware implementations of the block cipher AES. In the proposed scheme, the circuit component for the round function is divided into two stages, which are used alternately for encryption (or decryption) and error checking in a pipeline. The proposed scheme has a limited overhead with respect to size and speed for the following reasons. Firstly, the need for a double number of clock cycles is eliminated by virtue of the reduced critical path. Secondly, the scheme only requires minimal additional circuitry for error detection since the detection is performed by the remaining encryption (or decryption) components within the pipeline. AES hardware with the proposed scheme was designed and synthesized by using 90-nm CMOS standard cell library with various constraints. As a result, the proposed circuit achieved 1.66 Gbps @ 12.9 Kgates for the compact version and 4.22 Gbps @ 30.7 Kgates for the high-speed version. These performance characteristics are comparable to those of a basic AES circuit without error detection, where the overhead of the proposed scheme is estimated to be 14.5% at maximum. The proposed circuit was fabricated in the form of a chip, and its error detection performance was evaluated through experiments. The chip was tested with respect to fault injection by using clock glitch, and the proposed scheme successfully detected and reacted to all introduced errors.},
keywords={},
doi={10.1587/transfun.E94.A.1971},
ISSN={1745-1337},
month={October},}

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TY - JOUR
TI - High-Performance Architecture for Concurrent Error Detection for AES Processors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1971
EP - 1980
AU - Takeshi SUGAWARA
AU - Naofumi HOMMA
AU - Takafumi AOKI
AU - Akashi SATOH
PY - 2011
DO - 10.1587/transfun.E94.A.1971
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2011
AB - This paper proposes an efficient scheme for concurrent error detection for hardware implementations of the block cipher AES. In the proposed scheme, the circuit component for the round function is divided into two stages, which are used alternately for encryption (or decryption) and error checking in a pipeline. The proposed scheme has a limited overhead with respect to size and speed for the following reasons. Firstly, the need for a double number of clock cycles is eliminated by virtue of the reduced critical path. Secondly, the scheme only requires minimal additional circuitry for error detection since the detection is performed by the remaining encryption (or decryption) components within the pipeline. AES hardware with the proposed scheme was designed and synthesized by using 90-nm CMOS standard cell library with various constraints. As a result, the proposed circuit achieved 1.66 Gbps @ 12.9 Kgates for the compact version and 4.22 Gbps @ 30.7 Kgates for the high-speed version. These performance characteristics are comparable to those of a basic AES circuit without error detection, where the overhead of the proposed scheme is estimated to be 14.5% at maximum. The proposed circuit was fabricated in the form of a chip, and its error detection performance was evaluated through experiments. The chip was tested with respect to fault injection by using clock glitch, and the proposed scheme successfully detected and reacted to all introduced errors.
ER -