Multi-Operand Adder Synthesis Targeting FPGAs

Taeko MATSUNAGA; Shinji KIMURA; Yusuke MATSUNAGA

doi:10.1587/transfun.E94.A.2579

Multi-Operand Adder Synthesis Targeting FPGAs

Taeko MATSUNAGA, Shinji KIMURA, Yusuke MATSUNAGA

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Multi-operand adders, which calculates the summation of more than two operands, usually consist of compressor trees which reduce the number of operands to two without any carry propagation, and a carry-propagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters like Wallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on FPGAs is proposed. In case of FPGA with m-input LUT, any counters with up to m inputs can be realized with one LUT per an output. Our approach utilizes generalized parallel counters (GPCs) with up to m inputs and synthesizes high-performance compressor trees by setting some intermediate height limits in the compression process like Dadda's multipliers. Experimental results show that the number of GPCs are reduced by up to 22% compared to the existing heuristic. Its effectivity on reduction of delay is also shown against existing approaches on Altera's Stratix III.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.12 pp.2579-2586

Publication Date: 2011/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E94.A.2579

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Logic Synthesis, Test and Verification

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Taeko MATSUNAGA, Shinji KIMURA, Yusuke MATSUNAGA, "Multi-Operand Adder Synthesis Targeting FPGAs" in IEICE TRANSACTIONS on Fundamentals, vol. E94-A, no. 12, pp. 2579-2586, December 2011, doi: 10.1587/transfun.E94.A.2579.
Abstract: Multi-operand adders, which calculates the summation of more than two operands, usually consist of compressor trees which reduce the number of operands to two without any carry propagation, and a carry-propagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters like Wallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on FPGAs is proposed. In case of FPGA with m-input LUT, any counters with up to m inputs can be realized with one LUT per an output. Our approach utilizes generalized parallel counters (GPCs) with up to m inputs and synthesizes high-performance compressor trees by setting some intermediate height limits in the compression process like Dadda's multipliers. Experimental results show that the number of GPCs are reduced by up to 22% compared to the existing heuristic. Its effectivity on reduction of delay is also shown against existing approaches on Altera's Stratix III.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.2579/_p

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@ARTICLE{e94-a_12_2579,
author={Taeko MATSUNAGA, Shinji KIMURA, Yusuke MATSUNAGA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Multi-Operand Adder Synthesis Targeting FPGAs},
year={2011},
volume={E94-A},
number={12},
pages={2579-2586},
abstract={Multi-operand adders, which calculates the summation of more than two operands, usually consist of compressor trees which reduce the number of operands to two without any carry propagation, and a carry-propagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters like Wallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on FPGAs is proposed. In case of FPGA with m-input LUT, any counters with up to m inputs can be realized with one LUT per an output. Our approach utilizes generalized parallel counters (GPCs) with up to m inputs and synthesizes high-performance compressor trees by setting some intermediate height limits in the compression process like Dadda's multipliers. Experimental results show that the number of GPCs are reduced by up to 22% compared to the existing heuristic. Its effectivity on reduction of delay is also shown against existing approaches on Altera's Stratix III.},
keywords={},
doi={10.1587/transfun.E94.A.2579},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Multi-Operand Adder Synthesis Targeting FPGAs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2579
EP - 2586
AU - Taeko MATSUNAGA
AU - Shinji KIMURA
AU - Yusuke MATSUNAGA
PY - 2011
DO - 10.1587/transfun.E94.A.2579
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2011
AB - Multi-operand adders, which calculates the summation of more than two operands, usually consist of compressor trees which reduce the number of operands to two without any carry propagation, and a carry-propagate adder for the two operands in ASIC implementation. The former part is usually realized using full adders or (3;2) counters like Wallace-trees in ASIC, while adder trees or dedicated hardware are used in FPGA. In this paper, an approach to realize compression trees on FPGAs is proposed. In case of FPGA with m-input LUT, any counters with up to m inputs can be realized with one LUT per an output. Our approach utilizes generalized parallel counters (GPCs) with up to m inputs and synthesizes high-performance compressor trees by setting some intermediate height limits in the compression process like Dadda's multipliers. Experimental results show that the number of GPCs are reduced by up to 22% compared to the existing heuristic. Its effectivity on reduction of delay is also shown against existing approaches on Altera's Stratix III.
ER -