IEICE TRANSACTIONS on Fundamentals
An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer
Summary :
In this paper, an improved hybrid LUT-based architecture for low-error and efficient fixed-width squarer circuits is presented in which LUT-based and conventional logic circuits are employed together to achieve the good trade-off between hardware complexity and performance. By exploiting the mathematical identities and hybrid architecture, the mean error and mean squarer error of the proposed squarer are reduced by up to 40%, compared with the best previous method presented in literature. Moreover, the proposed method can improve the speed and reduce the area of the squarer circuit. The implementation and chip measurement results in 0.18-µm CMOS technology are also presented and discussed.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.7 pp.1180-1184
- Publication Date
- 2012/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.1180
- Type of Manuscript
- LETTER
- Category
- Digital Signal Processing
Authors
Keyword
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Van-Phuc HOANG, Cong-Kha PHAM, "An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 7, pp. 1180-1184, July 2012, doi: 10.1587/transfun.E95.A.1180.
Abstract: In this paper, an improved hybrid LUT-based architecture for low-error and efficient fixed-width squarer circuits is presented in which LUT-based and conventional logic circuits are employed together to achieve the good trade-off between hardware complexity and performance. By exploiting the mathematical identities and hybrid architecture, the mean error and mean squarer error of the proposed squarer are reduced by up to 40%, compared with the best previous method presented in literature. Moreover, the proposed method can improve the speed and reduce the area of the squarer circuit. The implementation and chip measurement results in 0.18-µm CMOS technology are also presented and discussed.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.1180/_p
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@ARTICLE{e95-a_7_1180,
author={Van-Phuc HOANG, Cong-Kha PHAM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer},
year={2012},
volume={E95-A},
number={7},
pages={1180-1184},
abstract={In this paper, an improved hybrid LUT-based architecture for low-error and efficient fixed-width squarer circuits is presented in which LUT-based and conventional logic circuits are employed together to achieve the good trade-off between hardware complexity and performance. By exploiting the mathematical identities and hybrid architecture, the mean error and mean squarer error of the proposed squarer are reduced by up to 40%, compared with the best previous method presented in literature. Moreover, the proposed method can improve the speed and reduce the area of the squarer circuit. The implementation and chip measurement results in 0.18-µm CMOS technology are also presented and discussed.},
keywords={},
doi={10.1587/transfun.E95.A.1180},
ISSN={1745-1337},
month={July},}
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TY - JOUR
TI - An Improved Hybrid LUT-Based Architecture for Low-Error and Efficient Fixed-Width Squarer
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1180
EP - 1184
AU - Van-Phuc HOANG
AU - Cong-Kha PHAM
PY - 2012
DO - 10.1587/transfun.E95.A.1180
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2012
AB - In this paper, an improved hybrid LUT-based architecture for low-error and efficient fixed-width squarer circuits is presented in which LUT-based and conventional logic circuits are employed together to achieve the good trade-off between hardware complexity and performance. By exploiting the mathematical identities and hybrid architecture, the mean error and mean squarer error of the proposed squarer are reduced by up to 40%, compared with the best previous method presented in literature. Moreover, the proposed method can improve the speed and reduce the area of the squarer circuit. The implementation and chip measurement results in 0.18-µm CMOS technology are also presented and discussed.
ER -
English
