IEICE TRANSACTIONS on Fundamentals
A Multi-Gigabit Parallel Demodulator and Its FPGA Implementation
Summary :
This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. Besides, in the demonstration of 2 Gbps demodulator for 16QAM modulation, the architecture is implemented and validated on a Xilinx V6 FPGA platform with performance loss less than 2 dB.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.8 pp.1412-1415
- Publication Date
- 2012/08/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.1412
- Type of Manuscript
- LETTER
- Category
- Digital Signal Processing
Authors
Keyword
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Changxing LIN, Jian ZHANG, Beibei SHAO, "A Multi-Gigabit Parallel Demodulator and Its FPGA Implementation" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 8, pp. 1412-1415, August 2012, doi: 10.1587/transfun.E95.A.1412.
Abstract: This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. Besides, in the demonstration of 2 Gbps demodulator for 16QAM modulation, the architecture is implemented and validated on a Xilinx V6 FPGA platform with performance loss less than 2 dB.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.1412/_p
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@ARTICLE{e95-a_8_1412,
author={Changxing LIN, Jian ZHANG, Beibei SHAO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Multi-Gigabit Parallel Demodulator and Its FPGA Implementation},
year={2012},
volume={E95-A},
number={8},
pages={1412-1415},
abstract={This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. Besides, in the demonstration of 2 Gbps demodulator for 16QAM modulation, the architecture is implemented and validated on a Xilinx V6 FPGA platform with performance loss less than 2 dB.},
keywords={},
doi={10.1587/transfun.E95.A.1412},
ISSN={1745-1337},
month={August},}
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TY - JOUR
TI - A Multi-Gigabit Parallel Demodulator and Its FPGA Implementation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1412
EP - 1415
AU - Changxing LIN
AU - Jian ZHANG
AU - Beibei SHAO
PY - 2012
DO - 10.1587/transfun.E95.A.1412
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2012
AB - This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. Besides, in the demonstration of 2 Gbps demodulator for 16QAM modulation, the architecture is implemented and validated on a Xilinx V6 FPGA platform with performance loss less than 2 dB.
ER -
English
