IEICE TRANSACTIONS on Fundamentals
Region Oriented Routing FPGA Architecture for Dynamic Power Gating
Summary :
Dynamic power gating applicable to FPGA can reduce the power consumption effectively. In this paper, we propose a sophisticated routing architecture for a region oriented FPGA which supports dynamic power gating. This is the first routing solution of dynamic power gating for coarse-grained FPGA. This paper has 2 main contributions. First, it improves the routing resource graph and routing architecture to support special routing for a region oriented FPGA. Second, some routing channels are made wider to avoid congestion. Experimental result shows that 7.7% routing area can be reduced compared with the symmetric Wilton switch box in the region. Also, our proposed FPGA architecture with sophisticated P&R can reduce the power consumption of the system implemented in FPGA.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.12 pp.2199-2207
- Publication Date
- 2012/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.2199
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Physical Level Design
Authors
Keyword
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Ce LI, Yiping DONG, Takahiro WATANABE, "Region Oriented Routing FPGA Architecture for Dynamic Power Gating" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 12, pp. 2199-2207, December 2012, doi: 10.1587/transfun.E95.A.2199.
Abstract: Dynamic power gating applicable to FPGA can reduce the power consumption effectively. In this paper, we propose a sophisticated routing architecture for a region oriented FPGA which supports dynamic power gating. This is the first routing solution of dynamic power gating for coarse-grained FPGA. This paper has 2 main contributions. First, it improves the routing resource graph and routing architecture to support special routing for a region oriented FPGA. Second, some routing channels are made wider to avoid congestion. Experimental result shows that 7.7% routing area can be reduced compared with the symmetric Wilton switch box in the region. Also, our proposed FPGA architecture with sophisticated P&R can reduce the power consumption of the system implemented in FPGA.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.2199/_p
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@ARTICLE{e95-a_12_2199,
author={Ce LI, Yiping DONG, Takahiro WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Region Oriented Routing FPGA Architecture for Dynamic Power Gating},
year={2012},
volume={E95-A},
number={12},
pages={2199-2207},
abstract={Dynamic power gating applicable to FPGA can reduce the power consumption effectively. In this paper, we propose a sophisticated routing architecture for a region oriented FPGA which supports dynamic power gating. This is the first routing solution of dynamic power gating for coarse-grained FPGA. This paper has 2 main contributions. First, it improves the routing resource graph and routing architecture to support special routing for a region oriented FPGA. Second, some routing channels are made wider to avoid congestion. Experimental result shows that 7.7% routing area can be reduced compared with the symmetric Wilton switch box in the region. Also, our proposed FPGA architecture with sophisticated P&R can reduce the power consumption of the system implemented in FPGA.},
keywords={},
doi={10.1587/transfun.E95.A.2199},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Region Oriented Routing FPGA Architecture for Dynamic Power Gating
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2199
EP - 2207
AU - Ce LI
AU - Yiping DONG
AU - Takahiro WATANABE
PY - 2012
DO - 10.1587/transfun.E95.A.2199
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2012
AB - Dynamic power gating applicable to FPGA can reduce the power consumption effectively. In this paper, we propose a sophisticated routing architecture for a region oriented FPGA which supports dynamic power gating. This is the first routing solution of dynamic power gating for coarse-grained FPGA. This paper has 2 main contributions. First, it improves the routing resource graph and routing architecture to support special routing for a region oriented FPGA. Second, some routing channels are made wider to avoid congestion. Experimental result shows that 7.7% routing area can be reduced compared with the symmetric Wilton switch box in the region. Also, our proposed FPGA architecture with sophisticated P&R can reduce the power consumption of the system implemented in FPGA.
ER -
English
