Glitch PUF: Extracting Information from Usually Unwanted Glitches
Summary :
In this paper, we propose a new Delay PUF architecture trying to solve the major problem of existing Delay PUFs that it is easy to predict the relation between delay information and generated information. For that purpose, our architecture exploits glitches as a source of information generation that behave non-linearly from delay variation between gates and the characteristic of pulse propagation of each gate. We thus call it the Glitch PUF. We present two circuit structures of the Glitch PUF both of which have their own merits. We then provide the results of evaluation in which we first verify that the two Glitch PUFs exhibit the same characteristics, and second show the randomness and statistical properties of the Glitch PUF.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.1 pp.223-233
- Publication Date
- 2012/01/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.223
- Type of Manuscript
- Special Section PAPER (Special Section on Cryptography and Information Security)
- Category
- Implementation
Authors
Keyword
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Koichi SHIMIZU, Daisuke SUZUKI, Tomomi KASUYA, "Glitch PUF: Extracting Information from Usually Unwanted Glitches" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 1, pp. 223-233, January 2012, doi: 10.1587/transfun.E95.A.223.
Abstract: In this paper, we propose a new Delay PUF architecture trying to solve the major problem of existing Delay PUFs that it is easy to predict the relation between delay information and generated information. For that purpose, our architecture exploits glitches as a source of information generation that behave non-linearly from delay variation between gates and the characteristic of pulse propagation of each gate. We thus call it the Glitch PUF. We present two circuit structures of the Glitch PUF both of which have their own merits. We then provide the results of evaluation in which we first verify that the two Glitch PUFs exhibit the same characteristics, and second show the randomness and statistical properties of the Glitch PUF.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.223/_p
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@ARTICLE{e95-a_1_223,
author={Koichi SHIMIZU, Daisuke SUZUKI, Tomomi KASUYA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Glitch PUF: Extracting Information from Usually Unwanted Glitches},
year={2012},
volume={E95-A},
number={1},
pages={223-233},
abstract={In this paper, we propose a new Delay PUF architecture trying to solve the major problem of existing Delay PUFs that it is easy to predict the relation between delay information and generated information. For that purpose, our architecture exploits glitches as a source of information generation that behave non-linearly from delay variation between gates and the characteristic of pulse propagation of each gate. We thus call it the Glitch PUF. We present two circuit structures of the Glitch PUF both of which have their own merits. We then provide the results of evaluation in which we first verify that the two Glitch PUFs exhibit the same characteristics, and second show the randomness and statistical properties of the Glitch PUF.},
keywords={},
doi={10.1587/transfun.E95.A.223},
ISSN={1745-1337},
month={January},}
Copy
TY - JOUR
TI - Glitch PUF: Extracting Information from Usually Unwanted Glitches
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 223
EP - 233
AU - Koichi SHIMIZU
AU - Daisuke SUZUKI
AU - Tomomi KASUYA
PY - 2012
DO - 10.1587/transfun.E95.A.223
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2012
AB - In this paper, we propose a new Delay PUF architecture trying to solve the major problem of existing Delay PUFs that it is easy to predict the relation between delay information and generated information. For that purpose, our architecture exploits glitches as a source of information generation that behave non-linearly from delay variation between gates and the characteristic of pulse propagation of each gate. We thus call it the Glitch PUF. We present two circuit structures of the Glitch PUF both of which have their own merits. We then provide the results of evaluation in which we first verify that the two Glitch PUFs exhibit the same characteristics, and second show the randomness and statistical properties of the Glitch PUF.
ER -
English
