Transaction Ordering in Network-on-Chips for Post-Silicon Validation

Amir Masoud GHAREHBAGHI; Masahiro FUJITA

doi:10.1587/transfun.E95.A.2309

Transaction Ordering in Network-on-Chips for Post-Silicon Validation

Amir Masoud GHAREHBAGHI, Masahiro FUJITA

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In this paper, we have addressed the problem of ordering transactions in network-on-chips (NoCs) for post-silicon validation. The main idea is to extract the order of the transactions from the local partial orders in each NoC tile based on a set of “happened-before” rules, assuming transactions do not have a timestamp. The assumption is based on the fact that implementation and usage of a global time as timestamp in such systems may not be practical or efficient. When a new transaction is received in a tile, we send special messages to the neighboring tiles to inform them regarding the new transaction. The process of sending those special messages continues recursively in all the tiles that receive them until another such special message is detected. This way, we relate local orders of different tiles with each other. We show that our method can reconstruct the correct transaction orders when communication delays are deterministic. We have shown the effectiveness of our method by correctly ordering the transaction in NoCs with mesh and torus topologies with different sizes from 5*5 to 9*9. Also, we have implemented the proposed method in hardware to show its feasibility.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.12 pp.2309-2318

Publication Date: 2012/12/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E95.A.2309

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Logic Synthesis, Test and Verification

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Amir Masoud GHAREHBAGHI, Masahiro FUJITA, "Transaction Ordering in Network-on-Chips for Post-Silicon Validation" in IEICE TRANSACTIONS on Fundamentals, vol. E95-A, no. 12, pp. 2309-2318, December 2012, doi: 10.1587/transfun.E95.A.2309.
Abstract: In this paper, we have addressed the problem of ordering transactions in network-on-chips (NoCs) for post-silicon validation. The main idea is to extract the order of the transactions from the local partial orders in each NoC tile based on a set of “happened-before” rules, assuming transactions do not have a timestamp. The assumption is based on the fact that implementation and usage of a global time as timestamp in such systems may not be practical or efficient. When a new transaction is received in a tile, we send special messages to the neighboring tiles to inform them regarding the new transaction. The process of sending those special messages continues recursively in all the tiles that receive them until another such special message is detected. This way, we relate local orders of different tiles with each other. We show that our method can reconstruct the correct transaction orders when communication delays are deterministic. We have shown the effectiveness of our method by correctly ordering the transaction in NoCs with mesh and torus topologies with different sizes from 5*5 to 9*9. Also, we have implemented the proposed method in hardware to show its feasibility.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.2309/_p

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@ARTICLE{e95-a_12_2309,
author={Amir Masoud GHAREHBAGHI, Masahiro FUJITA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Transaction Ordering in Network-on-Chips for Post-Silicon Validation},
year={2012},
volume={E95-A},
number={12},
pages={2309-2318},
abstract={In this paper, we have addressed the problem of ordering transactions in network-on-chips (NoCs) for post-silicon validation. The main idea is to extract the order of the transactions from the local partial orders in each NoC tile based on a set of “happened-before” rules, assuming transactions do not have a timestamp. The assumption is based on the fact that implementation and usage of a global time as timestamp in such systems may not be practical or efficient. When a new transaction is received in a tile, we send special messages to the neighboring tiles to inform them regarding the new transaction. The process of sending those special messages continues recursively in all the tiles that receive them until another such special message is detected. This way, we relate local orders of different tiles with each other. We show that our method can reconstruct the correct transaction orders when communication delays are deterministic. We have shown the effectiveness of our method by correctly ordering the transaction in NoCs with mesh and torus topologies with different sizes from 5*5 to 9*9. Also, we have implemented the proposed method in hardware to show its feasibility.},
keywords={},
doi={10.1587/transfun.E95.A.2309},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Transaction Ordering in Network-on-Chips for Post-Silicon Validation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2309
EP - 2318
AU - Amir Masoud GHAREHBAGHI
AU - Masahiro FUJITA
PY - 2012
DO - 10.1587/transfun.E95.A.2309
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2012
AB - In this paper, we have addressed the problem of ordering transactions in network-on-chips (NoCs) for post-silicon validation. The main idea is to extract the order of the transactions from the local partial orders in each NoC tile based on a set of “happened-before” rules, assuming transactions do not have a timestamp. The assumption is based on the fact that implementation and usage of a global time as timestamp in such systems may not be practical or efficient. When a new transaction is received in a tile, we send special messages to the neighboring tiles to inform them regarding the new transaction. The process of sending those special messages continues recursively in all the tiles that receive them until another such special message is detected. This way, we relate local orders of different tiles with each other. We show that our method can reconstruct the correct transaction orders when communication delays are deterministic. We have shown the effectiveness of our method by correctly ordering the transaction in NoCs with mesh and torus topologies with different sizes from 5*5 to 9*9. Also, we have implemented the proposed method in hardware to show its feasibility.
ER -