IEICE TRANSACTIONS on Fundamentals
A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing
Summary :
Emerging image and video applications and conventional MPSoC architectures encounter drastically increasing performance and flexibility requirements. In order to display high quality images, large amount of image processing needs to be carried out. These image processing algorithms are nonstandard and vary case by case, and it is difficult to achieve real time processing by using general purpose processors or DSP. In this paper, we present two reconfigurable Application Specific Instruction-set Processors (ASIP) which can perform several image processing algorithms by using the same processor architecture. These ASIPs can achieve performance similar to DSP; meanwhile, while the area is considerably smaller than DSP and slightly bigger than conventional RISC processor. 1D ASIP can perform 16 times higher compared to a RISC processor, and 2D ASIP can perform 3 to 7 times higher compared to a RISC processor.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.12 pp.2373-2383
- Publication Date
- 2012/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.2373
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- High-Level Synthesis and System-Level Design
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Keyword
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Hsuan-Chun LIAO, Mochamad ASRI, Tsuyoshi ISSHIKI, Dongju LI, Hiroaki KUNIEDA, "A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 12, pp. 2373-2383, December 2012, doi: 10.1587/transfun.E95.A.2373.
Abstract: Emerging image and video applications and conventional MPSoC architectures encounter drastically increasing performance and flexibility requirements. In order to display high quality images, large amount of image processing needs to be carried out. These image processing algorithms are nonstandard and vary case by case, and it is difficult to achieve real time processing by using general purpose processors or DSP. In this paper, we present two reconfigurable Application Specific Instruction-set Processors (ASIP) which can perform several image processing algorithms by using the same processor architecture. These ASIPs can achieve performance similar to DSP; meanwhile, while the area is considerably smaller than DSP and slightly bigger than conventional RISC processor. 1D ASIP can perform 16 times higher compared to a RISC processor, and 2D ASIP can perform 3 to 7 times higher compared to a RISC processor.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.2373/_p
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@ARTICLE{e95-a_12_2373,
author={Hsuan-Chun LIAO, Mochamad ASRI, Tsuyoshi ISSHIKI, Dongju LI, Hiroaki KUNIEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing},
year={2012},
volume={E95-A},
number={12},
pages={2373-2383},
abstract={Emerging image and video applications and conventional MPSoC architectures encounter drastically increasing performance and flexibility requirements. In order to display high quality images, large amount of image processing needs to be carried out. These image processing algorithms are nonstandard and vary case by case, and it is difficult to achieve real time processing by using general purpose processors or DSP. In this paper, we present two reconfigurable Application Specific Instruction-set Processors (ASIP) which can perform several image processing algorithms by using the same processor architecture. These ASIPs can achieve performance similar to DSP; meanwhile, while the area is considerably smaller than DSP and slightly bigger than conventional RISC processor. 1D ASIP can perform 16 times higher compared to a RISC processor, and 2D ASIP can perform 3 to 7 times higher compared to a RISC processor.},
keywords={},
doi={10.1587/transfun.E95.A.2373},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2373
EP - 2383
AU - Hsuan-Chun LIAO
AU - Mochamad ASRI
AU - Tsuyoshi ISSHIKI
AU - Dongju LI
AU - Hiroaki KUNIEDA
PY - 2012
DO - 10.1587/transfun.E95.A.2373
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2012
AB - Emerging image and video applications and conventional MPSoC architectures encounter drastically increasing performance and flexibility requirements. In order to display high quality images, large amount of image processing needs to be carried out. These image processing algorithms are nonstandard and vary case by case, and it is difficult to achieve real time processing by using general purpose processors or DSP. In this paper, we present two reconfigurable Application Specific Instruction-set Processors (ASIP) which can perform several image processing algorithms by using the same processor architecture. These ASIPs can achieve performance similar to DSP; meanwhile, while the area is considerably smaller than DSP and slightly bigger than conventional RISC processor. 1D ASIP can perform 16 times higher compared to a RISC processor, and 2D ASIP can perform 3 to 7 times higher compared to a RISC processor.
ER -
English
