IEICE TRANSACTIONS on Fundamentals
A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX
Summary :
Structured quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted in many wireless communication standards, such as WiMAX, Wi-Fi and WPAN. To completely support the variable code rate (multi-rate) and variable code length (multi-length) implementation for universal applications, the partial-parallel layered LDPC decoder architecture is straightforward and widely used in the decoder design. In this paper, we propose a high parallel LDPC decoder architecture for WiMAX system with dedicated ASIC design. Different from the block by block decoding schedule in most partial-parallel layered architectures, all the messages within each layer are updated simultaneously in the proposed fully-parallel layered decoder architecture. Meanwhile, the message updating is separated into bit-serial style to reduce hardware complexity. A 6-bit implementation is adopted in the decoder chip, since simulations demonstrate that 6-bit quantization is the best trade-off between performance and complexity. Moreover, the two-layer concurrent processing technique is proposed to further increase the parallelism for low code rates. Implementation results show that the decoder chip saves 22.2% storage bits and only takes 24
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.12 pp.2384-2391
- Publication Date
- 2012/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.2384
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- High-Level Synthesis and System-Level Design
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Xiongxin ZHAO, Xiao PENG, Zhixiang CHEN, Dajiang ZHOU, Satoshi GOTO, "A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 12, pp. 2384-2391, December 2012, doi: 10.1587/transfun.E95.A.2384.
Abstract: Structured quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted in many wireless communication standards, such as WiMAX, Wi-Fi and WPAN. To completely support the variable code rate (multi-rate) and variable code length (multi-length) implementation for universal applications, the partial-parallel layered LDPC decoder architecture is straightforward and widely used in the decoder design. In this paper, we propose a high parallel LDPC decoder architecture for WiMAX system with dedicated ASIC design. Different from the block by block decoding schedule in most partial-parallel layered architectures, all the messages within each layer are updated simultaneously in the proposed fully-parallel layered decoder architecture. Meanwhile, the message updating is separated into bit-serial style to reduce hardware complexity. A 6-bit implementation is adopted in the decoder chip, since simulations demonstrate that 6-bit quantization is the best trade-off between performance and complexity. Moreover, the two-layer concurrent processing technique is proposed to further increase the parallelism for low code rates. Implementation results show that the decoder chip saves 22.2% storage bits and only takes 24
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.2384/_p
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@ARTICLE{e95-a_12_2384,
author={Xiongxin ZHAO, Xiao PENG, Zhixiang CHEN, Dajiang ZHOU, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX},
year={2012},
volume={E95-A},
number={12},
pages={2384-2391},
abstract={Structured quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted in many wireless communication standards, such as WiMAX, Wi-Fi and WPAN. To completely support the variable code rate (multi-rate) and variable code length (multi-length) implementation for universal applications, the partial-parallel layered LDPC decoder architecture is straightforward and widely used in the decoder design. In this paper, we propose a high parallel LDPC decoder architecture for WiMAX system with dedicated ASIC design. Different from the block by block decoding schedule in most partial-parallel layered architectures, all the messages within each layer are updated simultaneously in the proposed fully-parallel layered decoder architecture. Meanwhile, the message updating is separated into bit-serial style to reduce hardware complexity. A 6-bit implementation is adopted in the decoder chip, since simulations demonstrate that 6-bit quantization is the best trade-off between performance and complexity. Moreover, the two-layer concurrent processing technique is proposed to further increase the parallelism for low code rates. Implementation results show that the decoder chip saves 22.2% storage bits and only takes 24
keywords={},
doi={10.1587/transfun.E95.A.2384},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2384
EP - 2391
AU - Xiongxin ZHAO
AU - Xiao PENG
AU - Zhixiang CHEN
AU - Dajiang ZHOU
AU - Satoshi GOTO
PY - 2012
DO - 10.1587/transfun.E95.A.2384
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2012
AB - Structured quasi-cyclic low-density parity-check (QC-LDPC) codes have been adopted in many wireless communication standards, such as WiMAX, Wi-Fi and WPAN. To completely support the variable code rate (multi-rate) and variable code length (multi-length) implementation for universal applications, the partial-parallel layered LDPC decoder architecture is straightforward and widely used in the decoder design. In this paper, we propose a high parallel LDPC decoder architecture for WiMAX system with dedicated ASIC design. Different from the block by block decoding schedule in most partial-parallel layered architectures, all the messages within each layer are updated simultaneously in the proposed fully-parallel layered decoder architecture. Meanwhile, the message updating is separated into bit-serial style to reduce hardware complexity. A 6-bit implementation is adopted in the decoder chip, since simulations demonstrate that 6-bit quantization is the best trade-off between performance and complexity. Moreover, the two-layer concurrent processing technique is proposed to further increase the parallelism for low code rates. Implementation results show that the decoder chip saves 22.2% storage bits and only takes 24
ER -
English
