IEICE TRANSACTIONS on Fundamentals
A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments
Summary :
This paper presents a glitchy-clock generator integrated in FPGA for evaluating fault injection attacks and their countermeasures on cryptographic modules. The proposed generator exploits clock management capabilities, which are common in modern FPGAs, to generate clock signal with temporal voltage spike. The shape and timing of the glitchy-clock cycle are configurable at run time. The proposed generator can be embedded in a single FPGA without any external instrument (e.g., a pulse generator and a variable power supply). Such integration enables reliable and reproducible fault injection experiments. In this paper, we examine the characteristics of the proposed generator through experiments on Side-channel Attack Standard Evaluation Board (SASEBO). The result shows that the timing of the glitches can be controlled at the step of about 0.17 ns. We also demonstrate its application to the safe-error attack against an RSA processor.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.1 pp.263-266
- Publication Date
- 2012/01/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.263
- Type of Manuscript
- Special Section LETTER (Special Section on Cryptography and Information Security)
- Category
Authors
Keyword
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Sho ENDO, Takeshi SUGAWARA, Naofumi HOMMA, Takafumi AOKI, Akashi SATOH, "A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 1, pp. 263-266, January 2012, doi: 10.1587/transfun.E95.A.263.
Abstract: This paper presents a glitchy-clock generator integrated in FPGA for evaluating fault injection attacks and their countermeasures on cryptographic modules. The proposed generator exploits clock management capabilities, which are common in modern FPGAs, to generate clock signal with temporal voltage spike. The shape and timing of the glitchy-clock cycle are configurable at run time. The proposed generator can be embedded in a single FPGA without any external instrument (e.g., a pulse generator and a variable power supply). Such integration enables reliable and reproducible fault injection experiments. In this paper, we examine the characteristics of the proposed generator through experiments on Side-channel Attack Standard Evaluation Board (SASEBO). The result shows that the timing of the glitches can be controlled at the step of about 0.17 ns. We also demonstrate its application to the safe-error attack against an RSA processor.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.263/_p
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@ARTICLE{e95-a_1_263,
author={Sho ENDO, Takeshi SUGAWARA, Naofumi HOMMA, Takafumi AOKI, Akashi SATOH, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments},
year={2012},
volume={E95-A},
number={1},
pages={263-266},
abstract={This paper presents a glitchy-clock generator integrated in FPGA for evaluating fault injection attacks and their countermeasures on cryptographic modules. The proposed generator exploits clock management capabilities, which are common in modern FPGAs, to generate clock signal with temporal voltage spike. The shape and timing of the glitchy-clock cycle are configurable at run time. The proposed generator can be embedded in a single FPGA without any external instrument (e.g., a pulse generator and a variable power supply). Such integration enables reliable and reproducible fault injection experiments. In this paper, we examine the characteristics of the proposed generator through experiments on Side-channel Attack Standard Evaluation Board (SASEBO). The result shows that the timing of the glitches can be controlled at the step of about 0.17 ns. We also demonstrate its application to the safe-error attack against an RSA processor.},
keywords={},
doi={10.1587/transfun.E95.A.263},
ISSN={1745-1337},
month={January},}
Copy
TY - JOUR
TI - A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 263
EP - 266
AU - Sho ENDO
AU - Takeshi SUGAWARA
AU - Naofumi HOMMA
AU - Takafumi AOKI
AU - Akashi SATOH
PY - 2012
DO - 10.1587/transfun.E95.A.263
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2012
AB - This paper presents a glitchy-clock generator integrated in FPGA for evaluating fault injection attacks and their countermeasures on cryptographic modules. The proposed generator exploits clock management capabilities, which are common in modern FPGAs, to generate clock signal with temporal voltage spike. The shape and timing of the glitchy-clock cycle are configurable at run time. The proposed generator can be embedded in a single FPGA without any external instrument (e.g., a pulse generator and a variable power supply). Such integration enables reliable and reproducible fault injection experiments. In this paper, we examine the characteristics of the proposed generator through experiments on Side-channel Attack Standard Evaluation Board (SASEBO). The result shows that the timing of the glitches can be controlled at the step of about 0.17 ns. We also demonstrate its application to the safe-error attack against an RSA processor.
ER -
English
