IEICE TRANSACTIONS on Fundamentals
Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion
Summary :
High performance, low area multipliers are highly desired for modern and future DSP systems due to the increasing demand of high speed DSP applications. In this paper, we present an efficient architecture for an LUT-based truncated multiplier and its application in RGB to YCbCr color space conversion which can be used for digital TV, image and video processing systems. By employing an improved split LUT-based architecture and LUT optimization method, the proposed multiplier can reduce the value of area-delay product by up to 52% compared with other constant multiplier methods. The FPGA implementation of a color space conversion application employing the proposed multiplier also results in significant reduction of area-delay product of up to 48%.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.6 pp.999-1006
- Publication Date
- 2012/06/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.999
- Type of Manuscript
- PAPER
- Category
- Digital Signal Processing
Authors
Keyword
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Van-Phuc HOANG, Cong-Kha PHAM, "Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 6, pp. 999-1006, June 2012, doi: 10.1587/transfun.E95.A.999.
Abstract: High performance, low area multipliers are highly desired for modern and future DSP systems due to the increasing demand of high speed DSP applications. In this paper, we present an efficient architecture for an LUT-based truncated multiplier and its application in RGB to YCbCr color space conversion which can be used for digital TV, image and video processing systems. By employing an improved split LUT-based architecture and LUT optimization method, the proposed multiplier can reduce the value of area-delay product by up to 52% compared with other constant multiplier methods. The FPGA implementation of a color space conversion application employing the proposed multiplier also results in significant reduction of area-delay product of up to 48%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.999/_p
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@ARTICLE{e95-a_6_999,
author={Van-Phuc HOANG, Cong-Kha PHAM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion},
year={2012},
volume={E95-A},
number={6},
pages={999-1006},
abstract={High performance, low area multipliers are highly desired for modern and future DSP systems due to the increasing demand of high speed DSP applications. In this paper, we present an efficient architecture for an LUT-based truncated multiplier and its application in RGB to YCbCr color space conversion which can be used for digital TV, image and video processing systems. By employing an improved split LUT-based architecture and LUT optimization method, the proposed multiplier can reduce the value of area-delay product by up to 52% compared with other constant multiplier methods. The FPGA implementation of a color space conversion application employing the proposed multiplier also results in significant reduction of area-delay product of up to 48%.},
keywords={},
doi={10.1587/transfun.E95.A.999},
ISSN={1745-1337},
month={June},}
Copy
TY - JOUR
TI - Efficient LUT-Based Truncated Multiplier and Its Application in RGB to YCbCr Color Space Conversion
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 999
EP - 1006
AU - Van-Phuc HOANG
AU - Cong-Kha PHAM
PY - 2012
DO - 10.1587/transfun.E95.A.999
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2012
AB - High performance, low area multipliers are highly desired for modern and future DSP systems due to the increasing demand of high speed DSP applications. In this paper, we present an efficient architecture for an LUT-based truncated multiplier and its application in RGB to YCbCr color space conversion which can be used for digital TV, image and video processing systems. By employing an improved split LUT-based architecture and LUT optimization method, the proposed multiplier can reduce the value of area-delay product by up to 52% compared with other constant multiplier methods. The FPGA implementation of a color space conversion application employing the proposed multiplier also results in significant reduction of area-delay product of up to 48%.
ER -
English
