Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning

Katherine Shu-Min LI; Yingchieh HO; Liang-Bi CHEN

doi:10.1587/transfun.E96.A.2467

Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning

Katherine Shu-Min LI, Yingchieh HO, Liang-Bi CHEN

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Crosstalk-induced noise has become a key problem in interconnect optimization when technology improves, spacing diminishes, and coupling capacitance/inductance increases. Buffer insertion/sizing is one of the most effective and popular techniques to reduce interconnect delay and decouple coupling effects. It is traditionally applied to post-layout optimization. However, it is obviously infeasible to insert/size hundreds of thousands buffers during the post-layout stage when most routing regions are occupied. Therefore, it is desirable to incorporate buffer planning into floorplanning to ensure timing closure and design convergence. In this paper, we first derive formulae of buffer insertion for timing and noise optimization, and then apply the formulae to compute the feasible regions for inserting buffers to meet both timing and noise constraints. Experimental results show that our approach achieves an average success rate of 80.9% (78.2%) of nets meeting timing constraints alone (both timing and noise constraints) and consumes an average extra area of only 0.49% (0.66%) over the given floorplan, compared with the average success rate of 75.6% of nets meeting timing constraints alone and an extra area of 1.33% by the BBP method proposed previously.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.12 pp.2467-2474

Publication Date: 2013/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E96.A.2467

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Physical Level Design

Authors

Katherine Shu-Min LI
  National Sun Yat-Sen University
Yingchieh HO
  National Dong-Hwa University
Liang-Bi CHEN
  National Sun Yat-Sen University

Keyword

crosstalk, delay effects, insertion buffer, interconnect-driven floorplanning, noise-aware buffer planning

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Katherine Shu-Min LI, Yingchieh HO, Liang-Bi CHEN, "Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning" in IEICE TRANSACTIONS on Fundamentals, vol. E96-A, no. 12, pp. 2467-2474, December 2013, doi: 10.1587/transfun.E96.A.2467.
Abstract: Crosstalk-induced noise has become a key problem in interconnect optimization when technology improves, spacing diminishes, and coupling capacitance/inductance increases. Buffer insertion/sizing is one of the most effective and popular techniques to reduce interconnect delay and decouple coupling effects. It is traditionally applied to post-layout optimization. However, it is obviously infeasible to insert/size hundreds of thousands buffers during the post-layout stage when most routing regions are occupied. Therefore, it is desirable to incorporate buffer planning into floorplanning to ensure timing closure and design convergence. In this paper, we first derive formulae of buffer insertion for timing and noise optimization, and then apply the formulae to compute the feasible regions for inserting buffers to meet both timing and noise constraints. Experimental results show that our approach achieves an average success rate of 80.9% (78.2%) of nets meeting timing constraints alone (both timing and noise constraints) and consumes an average extra area of only 0.49% (0.66%) over the given floorplan, compared with the average success rate of 75.6% of nets meeting timing constraints alone and an extra area of 1.33% by the BBP method proposed previously.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.2467/_p

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@ARTICLE{e96-a_12_2467,
author={Katherine Shu-Min LI, Yingchieh HO, Liang-Bi CHEN, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning},
year={2013},
volume={E96-A},
number={12},
pages={2467-2474},
abstract={Crosstalk-induced noise has become a key problem in interconnect optimization when technology improves, spacing diminishes, and coupling capacitance/inductance increases. Buffer insertion/sizing is one of the most effective and popular techniques to reduce interconnect delay and decouple coupling effects. It is traditionally applied to post-layout optimization. However, it is obviously infeasible to insert/size hundreds of thousands buffers during the post-layout stage when most routing regions are occupied. Therefore, it is desirable to incorporate buffer planning into floorplanning to ensure timing closure and design convergence. In this paper, we first derive formulae of buffer insertion for timing and noise optimization, and then apply the formulae to compute the feasible regions for inserting buffers to meet both timing and noise constraints. Experimental results show that our approach achieves an average success rate of 80.9% (78.2%) of nets meeting timing constraints alone (both timing and noise constraints) and consumes an average extra area of only 0.49% (0.66%) over the given floorplan, compared with the average success rate of 75.6% of nets meeting timing constraints alone and an extra area of 1.33% by the BBP method proposed previously.},
keywords={},
doi={10.1587/transfun.E96.A.2467},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2467
EP - 2474
AU - Katherine Shu-Min LI
AU - Yingchieh HO
AU - Liang-Bi CHEN
PY - 2013
DO - 10.1587/transfun.E96.A.2467
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2013
AB - Crosstalk-induced noise has become a key problem in interconnect optimization when technology improves, spacing diminishes, and coupling capacitance/inductance increases. Buffer insertion/sizing is one of the most effective and popular techniques to reduce interconnect delay and decouple coupling effects. It is traditionally applied to post-layout optimization. However, it is obviously infeasible to insert/size hundreds of thousands buffers during the post-layout stage when most routing regions are occupied. Therefore, it is desirable to incorporate buffer planning into floorplanning to ensure timing closure and design convergence. In this paper, we first derive formulae of buffer insertion for timing and noise optimization, and then apply the formulae to compute the feasible regions for inserting buffers to meet both timing and noise constraints. Experimental results show that our approach achieves an average success rate of 80.9% (78.2%) of nets meeting timing constraints alone (both timing and noise constraints) and consumes an average extra area of only 0.49% (0.66%) over the given floorplan, compared with the average success rate of 75.6% of nets meeting timing constraints alone and an extra area of 1.33% by the BBP method proposed previously.
ER -