Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle
Summary :
This paper addresses a high-level synthesis (HLS) using dual-edge-triggered flip-flops (DETFFs) as memory elements. In DETFF-based HLS, the duty cycle becomes a manageable resource to improve the timing performance. To utilize the duty cycle radically, a programmable duty cycle (PDC) mechanism is built into this HLS, and captured by a new HLS task named PDC scheduling. As a first step toward DETFF-based HLS with PDC, the execution time minimization problem is formulated for given results of operation scheduling. A linear program is presented to solve this problem in polynomial time. As a next step, simultaneous operation scheduling and PDC scheduling problem for the same objective is tackled. A mixed integer linear programming-based (MILP) approach is presented to solve this problem. The experimental results show that the MILP can reduce the execution time for several benchmarks.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.12 pp.2689-2697
- Publication Date
- 2013/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.2689
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Keisuke INOUE
Kanazawa Technical College (KTC)
Mineo KANEKO
Japan Advanced Institute of Science and Technology (JAIST)
Keyword
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Keisuke INOUE, Mineo KANEKO, "Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 12, pp. 2689-2697, December 2013, doi: 10.1587/transfun.E96.A.2689.
Abstract: This paper addresses a high-level synthesis (HLS) using dual-edge-triggered flip-flops (DETFFs) as memory elements. In DETFF-based HLS, the duty cycle becomes a manageable resource to improve the timing performance. To utilize the duty cycle radically, a programmable duty cycle (PDC) mechanism is built into this HLS, and captured by a new HLS task named PDC scheduling. As a first step toward DETFF-based HLS with PDC, the execution time minimization problem is formulated for given results of operation scheduling. A linear program is presented to solve this problem in polynomial time. As a next step, simultaneous operation scheduling and PDC scheduling problem for the same objective is tackled. A mixed integer linear programming-based (MILP) approach is presented to solve this problem. The experimental results show that the MILP can reduce the execution time for several benchmarks.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.2689/_p
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@ARTICLE{e96-a_12_2689,
author={Keisuke INOUE, Mineo KANEKO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle},
year={2013},
volume={E96-A},
number={12},
pages={2689-2697},
abstract={This paper addresses a high-level synthesis (HLS) using dual-edge-triggered flip-flops (DETFFs) as memory elements. In DETFF-based HLS, the duty cycle becomes a manageable resource to improve the timing performance. To utilize the duty cycle radically, a programmable duty cycle (PDC) mechanism is built into this HLS, and captured by a new HLS task named PDC scheduling. As a first step toward DETFF-based HLS with PDC, the execution time minimization problem is formulated for given results of operation scheduling. A linear program is presented to solve this problem in polynomial time. As a next step, simultaneous operation scheduling and PDC scheduling problem for the same objective is tackled. A mixed integer linear programming-based (MILP) approach is presented to solve this problem. The experimental results show that the MILP can reduce the execution time for several benchmarks.},
keywords={},
doi={10.1587/transfun.E96.A.2689},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2689
EP - 2697
AU - Keisuke INOUE
AU - Mineo KANEKO
PY - 2013
DO - 10.1587/transfun.E96.A.2689
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2013
AB - This paper addresses a high-level synthesis (HLS) using dual-edge-triggered flip-flops (DETFFs) as memory elements. In DETFF-based HLS, the duty cycle becomes a manageable resource to improve the timing performance. To utilize the duty cycle radically, a programmable duty cycle (PDC) mechanism is built into this HLS, and captured by a new HLS task named PDC scheduling. As a first step toward DETFF-based HLS with PDC, the execution time minimization problem is formulated for given results of operation scheduling. A linear program is presented to solve this problem in polynomial time. As a next step, simultaneous operation scheduling and PDC scheduling problem for the same objective is tackled. A mixed integer linear programming-based (MILP) approach is presented to solve this problem. The experimental results show that the MILP can reduce the execution time for several benchmarks.
ER -
English
