IEICE TRANSACTIONS on Fundamentals
Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS
Summary :
In modern cryptographic systems, physical unclonable functions (PUFs) are efficient mechanisms for many security applications, which extract intrinsic random physical variations to generate secret keys. The classical PUFs mainly exhibit static challenge-response behaviors and generate static keys, while many practical cryptographic systems need reconfigurable PUFs which allow dynamic keys derived from the same circuit. In this paper, the concept of reconfigurable multi-port PUFs (RM-PUFs) is proposed. RM-PUFs not only allow updating the keys without physically replacement, but also generate multiple keys from different ports in one clock cycle. A practical RM-PUFs construction is designed based on asynchronous clock and fabricated in TSMC low-power 65 nm CMOS process. The area of test chip is 1.1 mm2, and the maximum clock frequency is 0.8 GHz at 1.2 V. The average power consumption is 27.6 mW at 27
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E96-A No.5 pp.963-970
- Publication Date
- 2013/05/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E96.A.963
- Type of Manuscript
- PAPER
- Category
- Cryptography and Information Security
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Keyword
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Pengjun WANG, Yuejun ZHANG, Jun HAN, Zhiyi YU, Yibo FAN, Zhang ZHANG, "Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS" in IEICE TRANSACTIONS on Fundamentals,
vol. E96-A, no. 5, pp. 963-970, May 2013, doi: 10.1587/transfun.E96.A.963.
Abstract: In modern cryptographic systems, physical unclonable functions (PUFs) are efficient mechanisms for many security applications, which extract intrinsic random physical variations to generate secret keys. The classical PUFs mainly exhibit static challenge-response behaviors and generate static keys, while many practical cryptographic systems need reconfigurable PUFs which allow dynamic keys derived from the same circuit. In this paper, the concept of reconfigurable multi-port PUFs (RM-PUFs) is proposed. RM-PUFs not only allow updating the keys without physically replacement, but also generate multiple keys from different ports in one clock cycle. A practical RM-PUFs construction is designed based on asynchronous clock and fabricated in TSMC low-power 65 nm CMOS process. The area of test chip is 1.1 mm2, and the maximum clock frequency is 0.8 GHz at 1.2 V. The average power consumption is 27.6 mW at 27
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E96.A.963/_p
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@ARTICLE{e96-a_5_963,
author={Pengjun WANG, Yuejun ZHANG, Jun HAN, Zhiyi YU, Yibo FAN, Zhang ZHANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS},
year={2013},
volume={E96-A},
number={5},
pages={963-970},
abstract={In modern cryptographic systems, physical unclonable functions (PUFs) are efficient mechanisms for many security applications, which extract intrinsic random physical variations to generate secret keys. The classical PUFs mainly exhibit static challenge-response behaviors and generate static keys, while many practical cryptographic systems need reconfigurable PUFs which allow dynamic keys derived from the same circuit. In this paper, the concept of reconfigurable multi-port PUFs (RM-PUFs) is proposed. RM-PUFs not only allow updating the keys without physically replacement, but also generate multiple keys from different ports in one clock cycle. A practical RM-PUFs construction is designed based on asynchronous clock and fabricated in TSMC low-power 65 nm CMOS process. The area of test chip is 1.1 mm2, and the maximum clock frequency is 0.8 GHz at 1.2 V. The average power consumption is 27.6 mW at 27
keywords={},
doi={10.1587/transfun.E96.A.963},
ISSN={1745-1337},
month={May},}
Copy
TY - JOUR
TI - Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 963
EP - 970
AU - Pengjun WANG
AU - Yuejun ZHANG
AU - Jun HAN
AU - Zhiyi YU
AU - Yibo FAN
AU - Zhang ZHANG
PY - 2013
DO - 10.1587/transfun.E96.A.963
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E96-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2013
AB - In modern cryptographic systems, physical unclonable functions (PUFs) are efficient mechanisms for many security applications, which extract intrinsic random physical variations to generate secret keys. The classical PUFs mainly exhibit static challenge-response behaviors and generate static keys, while many practical cryptographic systems need reconfigurable PUFs which allow dynamic keys derived from the same circuit. In this paper, the concept of reconfigurable multi-port PUFs (RM-PUFs) is proposed. RM-PUFs not only allow updating the keys without physically replacement, but also generate multiple keys from different ports in one clock cycle. A practical RM-PUFs construction is designed based on asynchronous clock and fabricated in TSMC low-power 65 nm CMOS process. The area of test chip is 1.1 mm2, and the maximum clock frequency is 0.8 GHz at 1.2 V. The average power consumption is 27.6 mW at 27
ER -
English
