Chosen-IV Correlation Power Analysis on KCipher-2 Hardware and a Masking-Based Countermeasure
Summary :
This paper presents a chosen-IV (Initial Vector) correlation power analysis on the international standard stream cipher KCipher-2 together with an effective countermeasure. First, we describe a power analysis technique which can reveal the secret key (initial key) of KCipher-2 and then evaluate the validity of the CPA with experiments using both FPGA and ASIC implementations of KCipher-2 processors. This paper also proposes a masking-based countermeasure against the CPA. The concept of the proposed countermeasure is to mask intermediate data which pass through the non-linear function part including integer addition, substitution functions, and internal registers L1 and L2. We design two types of masked integer adders and two types of masked substitution circuits in order to minimize circuit area and delay, respectively. The effectiveness of the countermeasure is demonstrated through an experiment on the same FPGA platform. The performance of the proposed method is evaluated through the ASIC fabricated by TSMC 65nm CMOS process technology. In comparison with the conventional design, the design with the countermeasure can be achieved by the area increase of 1.6 times at most.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E97-A No.1 pp.157-166
- Publication Date
- 2014/01/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E97.A.157
- Type of Manuscript
- Special Section PAPER (Special Section on Cryptography and Information Security)
- Category
- Symmetric Key Based Cryptography
Authors
Takafumi HIBIKI
Tohoku University
Naofumi HOMMA
Tohoku University
Yuto NAKANO
KDDI R&D Laboratories
Kazuhide FUKUSHIMA
KDDI R&D Laboratories
Shinsaku KIYOMOTO
KDDI R&D Laboratories
Yutaka MIYAKE
KDDI R&D Laboratories
Takafumi AOKI
Tohoku University
Keyword
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Takafumi HIBIKI, Naofumi HOMMA, Yuto NAKANO, Kazuhide FUKUSHIMA, Shinsaku KIYOMOTO, Yutaka MIYAKE, Takafumi AOKI, "Chosen-IV Correlation Power Analysis on KCipher-2 Hardware and a Masking-Based Countermeasure" in IEICE TRANSACTIONS on Fundamentals,
vol. E97-A, no. 1, pp. 157-166, January 2014, doi: 10.1587/transfun.E97.A.157.
Abstract: This paper presents a chosen-IV (Initial Vector) correlation power analysis on the international standard stream cipher KCipher-2 together with an effective countermeasure. First, we describe a power analysis technique which can reveal the secret key (initial key) of KCipher-2 and then evaluate the validity of the CPA with experiments using both FPGA and ASIC implementations of KCipher-2 processors. This paper also proposes a masking-based countermeasure against the CPA. The concept of the proposed countermeasure is to mask intermediate data which pass through the non-linear function part including integer addition, substitution functions, and internal registers L1 and L2. We design two types of masked integer adders and two types of masked substitution circuits in order to minimize circuit area and delay, respectively. The effectiveness of the countermeasure is demonstrated through an experiment on the same FPGA platform. The performance of the proposed method is evaluated through the ASIC fabricated by TSMC 65nm CMOS process technology. In comparison with the conventional design, the design with the countermeasure can be achieved by the area increase of 1.6 times at most.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E97.A.157/_p
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@ARTICLE{e97-a_1_157,
author={Takafumi HIBIKI, Naofumi HOMMA, Yuto NAKANO, Kazuhide FUKUSHIMA, Shinsaku KIYOMOTO, Yutaka MIYAKE, Takafumi AOKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Chosen-IV Correlation Power Analysis on KCipher-2 Hardware and a Masking-Based Countermeasure},
year={2014},
volume={E97-A},
number={1},
pages={157-166},
abstract={This paper presents a chosen-IV (Initial Vector) correlation power analysis on the international standard stream cipher KCipher-2 together with an effective countermeasure. First, we describe a power analysis technique which can reveal the secret key (initial key) of KCipher-2 and then evaluate the validity of the CPA with experiments using both FPGA and ASIC implementations of KCipher-2 processors. This paper also proposes a masking-based countermeasure against the CPA. The concept of the proposed countermeasure is to mask intermediate data which pass through the non-linear function part including integer addition, substitution functions, and internal registers L1 and L2. We design two types of masked integer adders and two types of masked substitution circuits in order to minimize circuit area and delay, respectively. The effectiveness of the countermeasure is demonstrated through an experiment on the same FPGA platform. The performance of the proposed method is evaluated through the ASIC fabricated by TSMC 65nm CMOS process technology. In comparison with the conventional design, the design with the countermeasure can be achieved by the area increase of 1.6 times at most.},
keywords={},
doi={10.1587/transfun.E97.A.157},
ISSN={1745-1337},
month={January},}
Copy
TY - JOUR
TI - Chosen-IV Correlation Power Analysis on KCipher-2 Hardware and a Masking-Based Countermeasure
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 157
EP - 166
AU - Takafumi HIBIKI
AU - Naofumi HOMMA
AU - Yuto NAKANO
AU - Kazuhide FUKUSHIMA
AU - Shinsaku KIYOMOTO
AU - Yutaka MIYAKE
AU - Takafumi AOKI
PY - 2014
DO - 10.1587/transfun.E97.A.157
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E97-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2014
AB - This paper presents a chosen-IV (Initial Vector) correlation power analysis on the international standard stream cipher KCipher-2 together with an effective countermeasure. First, we describe a power analysis technique which can reveal the secret key (initial key) of KCipher-2 and then evaluate the validity of the CPA with experiments using both FPGA and ASIC implementations of KCipher-2 processors. This paper also proposes a masking-based countermeasure against the CPA. The concept of the proposed countermeasure is to mask intermediate data which pass through the non-linear function part including integer addition, substitution functions, and internal registers L1 and L2. We design two types of masked integer adders and two types of masked substitution circuits in order to minimize circuit area and delay, respectively. The effectiveness of the countermeasure is demonstrated through an experiment on the same FPGA platform. The performance of the proposed method is evaluated through the ASIC fabricated by TSMC 65nm CMOS process technology. In comparison with the conventional design, the design with the countermeasure can be achieved by the area increase of 1.6 times at most.
ER -
English
