IEICE TRANSACTIONS on Fundamentals
Edge-over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm
Summary :
As VLSI process node continue to shrink, chemical mechanical planarization (CMP) process for copper interconnect has become an essential technique for enabling many-layer interconnection. Recently, Edge-over-Erosion error (EoE-error), which originates from overpolishing and could cause yield loss, is observed in various CMP processes, while its mechanism is still unclear. To predict these errors, we propose an EoE-error prediction method that exploits machine learning algorithms. The proposed method consists of (1) error analysis stage, (2) layout parameter extraction stage, (3) model construction stage and (4) prediction stage. In the error analysis and parameter extraction stages, we analyze test chips and identify layout parameters which have an impact on EoE phenomenon. In the model construction stage, we construct a prediction model using the proposed multi-level machine learning method, and do predictions for designed layouts in the prediction stage. Experimental results show that the proposed method attained 2.7∼19.2% accuracy improvement of EoE-error prediction and 0.8∼10.1% improvement of non-EoE-error prediction compared with general machine learning methods. The proposed method makes it possible to prevent unexpected yield loss by recognizing EoE-errors before manufacturing.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E97-A No.12 pp.2373-2382
- Publication Date
- 2014/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E97.A.2373
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Device and Circuit Modeling and Analysis
Authors
Daisuke FUKUDA
FUJITSU LABORATORIES LTD.,FUJITSU SEMICONDUCTOR LTD.
Kenichi WATANABE
Osaka University
Naoki IDANI
Osaka University
Yuji KANAZAWA
FUJITSU LABORATORIES LTD.
Masanori HASHIMOTO
FUJITSU SEMICONDUCTOR LTD.
Keyword
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Daisuke FUKUDA, Kenichi WATANABE, Naoki IDANI, Yuji KANAZAWA, Masanori HASHIMOTO, "Edge-over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm" in IEICE TRANSACTIONS on Fundamentals,
vol. E97-A, no. 12, pp. 2373-2382, December 2014, doi: 10.1587/transfun.E97.A.2373.
Abstract: As VLSI process node continue to shrink, chemical mechanical planarization (CMP) process for copper interconnect has become an essential technique for enabling many-layer interconnection. Recently, Edge-over-Erosion error (EoE-error), which originates from overpolishing and could cause yield loss, is observed in various CMP processes, while its mechanism is still unclear. To predict these errors, we propose an EoE-error prediction method that exploits machine learning algorithms. The proposed method consists of (1) error analysis stage, (2) layout parameter extraction stage, (3) model construction stage and (4) prediction stage. In the error analysis and parameter extraction stages, we analyze test chips and identify layout parameters which have an impact on EoE phenomenon. In the model construction stage, we construct a prediction model using the proposed multi-level machine learning method, and do predictions for designed layouts in the prediction stage. Experimental results show that the proposed method attained 2.7∼19.2% accuracy improvement of EoE-error prediction and 0.8∼10.1% improvement of non-EoE-error prediction compared with general machine learning methods. The proposed method makes it possible to prevent unexpected yield loss by recognizing EoE-errors before manufacturing.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E97.A.2373/_p
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@ARTICLE{e97-a_12_2373,
author={Daisuke FUKUDA, Kenichi WATANABE, Naoki IDANI, Yuji KANAZAWA, Masanori HASHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Edge-over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm},
year={2014},
volume={E97-A},
number={12},
pages={2373-2382},
abstract={As VLSI process node continue to shrink, chemical mechanical planarization (CMP) process for copper interconnect has become an essential technique for enabling many-layer interconnection. Recently, Edge-over-Erosion error (EoE-error), which originates from overpolishing and could cause yield loss, is observed in various CMP processes, while its mechanism is still unclear. To predict these errors, we propose an EoE-error prediction method that exploits machine learning algorithms. The proposed method consists of (1) error analysis stage, (2) layout parameter extraction stage, (3) model construction stage and (4) prediction stage. In the error analysis and parameter extraction stages, we analyze test chips and identify layout parameters which have an impact on EoE phenomenon. In the model construction stage, we construct a prediction model using the proposed multi-level machine learning method, and do predictions for designed layouts in the prediction stage. Experimental results show that the proposed method attained 2.7∼19.2% accuracy improvement of EoE-error prediction and 0.8∼10.1% improvement of non-EoE-error prediction compared with general machine learning methods. The proposed method makes it possible to prevent unexpected yield loss by recognizing EoE-errors before manufacturing.},
keywords={},
doi={10.1587/transfun.E97.A.2373},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Edge-over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2373
EP - 2382
AU - Daisuke FUKUDA
AU - Kenichi WATANABE
AU - Naoki IDANI
AU - Yuji KANAZAWA
AU - Masanori HASHIMOTO
PY - 2014
DO - 10.1587/transfun.E97.A.2373
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E97-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2014
AB - As VLSI process node continue to shrink, chemical mechanical planarization (CMP) process for copper interconnect has become an essential technique for enabling many-layer interconnection. Recently, Edge-over-Erosion error (EoE-error), which originates from overpolishing and could cause yield loss, is observed in various CMP processes, while its mechanism is still unclear. To predict these errors, we propose an EoE-error prediction method that exploits machine learning algorithms. The proposed method consists of (1) error analysis stage, (2) layout parameter extraction stage, (3) model construction stage and (4) prediction stage. In the error analysis and parameter extraction stages, we analyze test chips and identify layout parameters which have an impact on EoE phenomenon. In the model construction stage, we construct a prediction model using the proposed multi-level machine learning method, and do predictions for designed layouts in the prediction stage. Experimental results show that the proposed method attained 2.7∼19.2% accuracy improvement of EoE-error prediction and 0.8∼10.1% improvement of non-EoE-error prediction compared with general machine learning methods. The proposed method makes it possible to prevent unexpected yield loss by recognizing EoE-errors before manufacturing.
ER -
English
