Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation

Chin-Long WEY; Ping-Chang JUI; Gang-Neng SUNG

doi:10.1587/transfun.E97.A.616

Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation

Chin-Long WEY, Ping-Chang JUI, Gang-Neng SUNG

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This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and UCS for 3N and N/3 operations, respectively. For 3N operation, the UCA-based ripple carry adder (RCA) and carry lookahead adder (CLA) designs are proposed and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18µm CMOS process. Results show that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA-based RCA and even 25% faster than the FA-based CLA. The proposed 16-bit and 64-bit UCA-based CLAs are 62% and 36% faster than the conventional FA-based CLAs, respectively. For N/3 operations, ripple borrow subtractor (RBS) is also presented. The 16-bit UCS-based RBS is about 15.5% faster than the 16-bit FS-based RBS.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E97-A No.2 pp.616-623

Publication Date: 2014/02/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E97.A.616

Type of Manuscript: PAPER

Category: VLSI Design Technology and CAD

Authors

Chin-Long WEY
  National Chiao Tung University
Ping-Chang JUI
  National Central University
Gang-Neng SUNG
  National Applied Research Laboratories

Keyword

ripple carry adder (RCA), carry-lookahead adder (CLA), ripple-borrow subtractor (RBS), multiplier, divider

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Chin-Long WEY, Ping-Chang JUI, Gang-Neng SUNG, "Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation" in IEICE TRANSACTIONS on Fundamentals, vol. E97-A, no. 2, pp. 616-623, February 2014, doi: 10.1587/transfun.E97.A.616.
Abstract: This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and UCS for 3N and N/3 operations, respectively. For 3N operation, the UCA-based ripple carry adder (RCA) and carry lookahead adder (CLA) designs are proposed and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18µm CMOS process. Results show that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA-based RCA and even 25% faster than the FA-based CLA. The proposed 16-bit and 64-bit UCA-based CLAs are 62% and 36% faster than the conventional FA-based CLAs, respectively. For N/3 operations, ripple borrow subtractor (RBS) is also presented. The 16-bit UCS-based RBS is about 15.5% faster than the 16-bit FS-based RBS.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E97.A.616/_p

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@ARTICLE{e97-a_2_616,
author={Chin-Long WEY, Ping-Chang JUI, Gang-Neng SUNG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation},
year={2014},
volume={E97-A},
number={2},
pages={616-623},
abstract={This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and UCS for 3N and N/3 operations, respectively. For 3N operation, the UCA-based ripple carry adder (RCA) and carry lookahead adder (CLA) designs are proposed and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18µm CMOS process. Results show that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA-based RCA and even 25% faster than the FA-based CLA. The proposed 16-bit and 64-bit UCA-based CLAs are 62% and 36% faster than the conventional FA-based CLAs, respectively. For N/3 operations, ripple borrow subtractor (RBS) is also presented. The 16-bit UCS-based RBS is about 15.5% faster than the 16-bit FS-based RBS.},
keywords={},
doi={10.1587/transfun.E97.A.616},
ISSN={1745-1337},
month={February},}

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TY - JOUR
TI - Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 616
EP - 623
AU - Chin-Long WEY
AU - Ping-Chang JUI
AU - Gang-Neng SUNG
PY - 2014
DO - 10.1587/transfun.E97.A.616
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E97-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2014
AB - This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and UCS for 3N and N/3 operations, respectively. For 3N operation, the UCA-based ripple carry adder (RCA) and carry lookahead adder (CLA) designs are proposed and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18µm CMOS process. Results show that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA-based RCA and even 25% faster than the FA-based CLA. The proposed 16-bit and 64-bit UCA-based CLAs are 62% and 36% faster than the conventional FA-based CLAs, respectively. For N/3 operations, ripple borrow subtractor (RBS) is also presented. The 16-bit UCS-based RBS is about 15.5% faster than the 16-bit FS-based RBS.
ER -