IEICE TRANSACTIONS on Fundamentals
A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining
Summary :
Syndrome key equation solution is one of the important processes in the decoding of Reed-Solomon codes. This paper proposes a low power key equation solver (KES) architecture where the power consumption is reduced by decreasing the required number of multiplications without degrading the decoding throughput and latency. The proposed method employs smaller number of multipliers than a conventional low power KES architecture. The critical path in the proposed KES circuit is minimized so that the operation at a high clock frequency is possible. A low power folded KES architecture is also proposed to further reduce the hardware complexity by executing folded operations in a pipelined manner with a slight increase in decoding latency.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.5 pp.1058-1066
- Publication Date
- 2015/05/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.1058
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Kazuhito ITO
Saitama University
Keyword
Latest Issue
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Kazuhito ITO, "A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 5, pp. 1058-1066, May 2015, doi: 10.1587/transfun.E98.A.1058.
Abstract: Syndrome key equation solution is one of the important processes in the decoding of Reed-Solomon codes. This paper proposes a low power key equation solver (KES) architecture where the power consumption is reduced by decreasing the required number of multiplications without degrading the decoding throughput and latency. The proposed method employs smaller number of multipliers than a conventional low power KES architecture. The critical path in the proposed KES circuit is minimized so that the operation at a high clock frequency is possible. A low power folded KES architecture is also proposed to further reduce the hardware complexity by executing folded operations in a pipelined manner with a slight increase in decoding latency.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.1058/_p
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@ARTICLE{e98-a_5_1058,
author={Kazuhito ITO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining},
year={2015},
volume={E98-A},
number={5},
pages={1058-1066},
abstract={Syndrome key equation solution is one of the important processes in the decoding of Reed-Solomon codes. This paper proposes a low power key equation solver (KES) architecture where the power consumption is reduced by decreasing the required number of multiplications without degrading the decoding throughput and latency. The proposed method employs smaller number of multipliers than a conventional low power KES architecture. The critical path in the proposed KES circuit is minimized so that the operation at a high clock frequency is possible. A low power folded KES architecture is also proposed to further reduce the hardware complexity by executing folded operations in a pipelined manner with a slight increase in decoding latency.},
keywords={},
doi={10.1587/transfun.E98.A.1058},
ISSN={1745-1337},
month={May},}
Copy
TY - JOUR
TI - A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1058
EP - 1066
AU - Kazuhito ITO
PY - 2015
DO - 10.1587/transfun.E98.A.1058
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2015
AB - Syndrome key equation solution is one of the important processes in the decoding of Reed-Solomon codes. This paper proposes a low power key equation solver (KES) architecture where the power consumption is reduced by decreasing the required number of multiplications without degrading the decoding throughput and latency. The proposed method employs smaller number of multipliers than a conventional low power KES architecture. The critical path in the proposed KES circuit is minimized so that the operation at a high clock frequency is possible. A low power folded KES architecture is also proposed to further reduce the hardware complexity by executing folded operations in a pipelined manner with a slight increase in decoding latency.
ER -
English
