IEICE TRANSACTIONS on Fundamentals
Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding
Summary :
In this paper, VLSI architecture design of unified motion vector (MV) and boundary strength (BS) parameter decoder (PDec) for 8K UHDTV HEVC decoder is presented. The adoption of new coding tools in PDec, such as Advanced Motion Vector Prediction (AMVP), increases the VLSI hardware realization overhead and memory bandwidth requirement, especially for 8K UHDTV application. We propose four techniques for these challenges. Firstly, this work unifies MV and BS parameter decoders for line buffer memory sharing. Secondly, to support high throughput, we propose the top-level CU-adaptive pipeline scheme by trading off between implementation complexity and performance. Thirdly, PDec process engine with optimizations is adopted for 43.2k area reduction. Finally, PU-based coding scheme is proposed for 30% DRAM bandwidth reduction. In 90nm process, our design costs 93.3k logic gates with 23.0kB line buffer. The proposed architecture can support real-time decoding for 7680x4320@60fps application at 249MHz in the worst case.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.7 pp.1356-1365
- Publication Date
- 2015/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.1356
- Type of Manuscript
- Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
- Category
Authors
Shihao WANG
Waseda Univ.
Dajiang ZHOU
Waseda Univ.
Jianbin ZHOU
Waseda Univ.
Takeshi YOSHIMURA
Waseda Univ.
Satoshi GOTO
Waseda Univ.
Keyword
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Shihao WANG, Dajiang ZHOU, Jianbin ZHOU, Takeshi YOSHIMURA, Satoshi GOTO, "Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 7, pp. 1356-1365, July 2015, doi: 10.1587/transfun.E98.A.1356.
Abstract: In this paper, VLSI architecture design of unified motion vector (MV) and boundary strength (BS) parameter decoder (PDec) for 8K UHDTV HEVC decoder is presented. The adoption of new coding tools in PDec, such as Advanced Motion Vector Prediction (AMVP), increases the VLSI hardware realization overhead and memory bandwidth requirement, especially for 8K UHDTV application. We propose four techniques for these challenges. Firstly, this work unifies MV and BS parameter decoders for line buffer memory sharing. Secondly, to support high throughput, we propose the top-level CU-adaptive pipeline scheme by trading off between implementation complexity and performance. Thirdly, PDec process engine with optimizations is adopted for 43.2k area reduction. Finally, PU-based coding scheme is proposed for 30% DRAM bandwidth reduction. In 90nm process, our design costs 93.3k logic gates with 23.0kB line buffer. The proposed architecture can support real-time decoding for 7680x4320@60fps application at 249MHz in the worst case.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.1356/_p
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@ARTICLE{e98-a_7_1356,
author={Shihao WANG, Dajiang ZHOU, Jianbin ZHOU, Takeshi YOSHIMURA, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding},
year={2015},
volume={E98-A},
number={7},
pages={1356-1365},
abstract={In this paper, VLSI architecture design of unified motion vector (MV) and boundary strength (BS) parameter decoder (PDec) for 8K UHDTV HEVC decoder is presented. The adoption of new coding tools in PDec, such as Advanced Motion Vector Prediction (AMVP), increases the VLSI hardware realization overhead and memory bandwidth requirement, especially for 8K UHDTV application. We propose four techniques for these challenges. Firstly, this work unifies MV and BS parameter decoders for line buffer memory sharing. Secondly, to support high throughput, we propose the top-level CU-adaptive pipeline scheme by trading off between implementation complexity and performance. Thirdly, PDec process engine with optimizations is adopted for 43.2k area reduction. Finally, PU-based coding scheme is proposed for 30% DRAM bandwidth reduction. In 90nm process, our design costs 93.3k logic gates with 23.0kB line buffer. The proposed architecture can support real-time decoding for 7680x4320@60fps application at 249MHz in the worst case.},
keywords={},
doi={10.1587/transfun.E98.A.1356},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - Unified Parameter Decoder Architecture for H.265/HEVC Motion Vector and Boundary Strength Decoding
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1356
EP - 1365
AU - Shihao WANG
AU - Dajiang ZHOU
AU - Jianbin ZHOU
AU - Takeshi YOSHIMURA
AU - Satoshi GOTO
PY - 2015
DO - 10.1587/transfun.E98.A.1356
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2015
AB - In this paper, VLSI architecture design of unified motion vector (MV) and boundary strength (BS) parameter decoder (PDec) for 8K UHDTV HEVC decoder is presented. The adoption of new coding tools in PDec, such as Advanced Motion Vector Prediction (AMVP), increases the VLSI hardware realization overhead and memory bandwidth requirement, especially for 8K UHDTV application. We propose four techniques for these challenges. Firstly, this work unifies MV and BS parameter decoders for line buffer memory sharing. Secondly, to support high throughput, we propose the top-level CU-adaptive pipeline scheme by trading off between implementation complexity and performance. Thirdly, PDec process engine with optimizations is adopted for 43.2k area reduction. Finally, PU-based coding scheme is proposed for 30% DRAM bandwidth reduction. In 90nm process, our design costs 93.3k logic gates with 23.0kB line buffer. The proposed architecture can support real-time decoding for 7680x4320@60fps application at 249MHz in the worst case.
ER -
English
