IEICE TRANSACTIONS on Fundamentals
An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design
Summary :
In this paper, we first propose an HDR-mcd architecture, which integrates periodically all-in-phase based multiple clock domains and multi-cycle interconnect communication into high-level synthesis. In HDR-mcd, an entire chip is divided into several huddles. Huddles can realize synchronization between different clock domains in which interconnection delay should be considered during high-level synthesis. Next, we propose a high-level synthesis algorithm for HDR-mcd, which can reduce energy consumption by optimizing configuration and placement of huddles. Experimental results show that the proposed method achieves 32.5% energy-saving compared with the existing single clock domain based methods.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.7 pp.1376-1391
- Publication Date
- 2015/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.1376
- Type of Manuscript
- Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
- Category
Authors
Shin-ya ABE
Waseda University
Youhua SHI
Waseda University
Kimiyoshi USAMI
Waseda University,Shibaura Institute of Technology,Waseda University
Masao YANAGISAWA
Waseda University
Nozomu TOGAWA
Waseda University
Keyword
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Shin-ya ABE, Youhua SHI, Kimiyoshi USAMI, Masao YANAGISAWA, Nozomu TOGAWA, "An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 7, pp. 1376-1391, July 2015, doi: 10.1587/transfun.E98.A.1376.
Abstract: In this paper, we first propose an HDR-mcd architecture, which integrates periodically all-in-phase based multiple clock domains and multi-cycle interconnect communication into high-level synthesis. In HDR-mcd, an entire chip is divided into several huddles. Huddles can realize synchronization between different clock domains in which interconnection delay should be considered during high-level synthesis. Next, we propose a high-level synthesis algorithm for HDR-mcd, which can reduce energy consumption by optimizing configuration and placement of huddles. Experimental results show that the proposed method achieves 32.5% energy-saving compared with the existing single clock domain based methods.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.1376/_p
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@ARTICLE{e98-a_7_1376,
author={Shin-ya ABE, Youhua SHI, Kimiyoshi USAMI, Masao YANAGISAWA, Nozomu TOGAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design},
year={2015},
volume={E98-A},
number={7},
pages={1376-1391},
abstract={In this paper, we first propose an HDR-mcd architecture, which integrates periodically all-in-phase based multiple clock domains and multi-cycle interconnect communication into high-level synthesis. In HDR-mcd, an entire chip is divided into several huddles. Huddles can realize synchronization between different clock domains in which interconnection delay should be considered during high-level synthesis. Next, we propose a high-level synthesis algorithm for HDR-mcd, which can reduce energy consumption by optimizing configuration and placement of huddles. Experimental results show that the proposed method achieves 32.5% energy-saving compared with the existing single clock domain based methods.},
keywords={},
doi={10.1587/transfun.E98.A.1376},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1376
EP - 1391
AU - Shin-ya ABE
AU - Youhua SHI
AU - Kimiyoshi USAMI
AU - Masao YANAGISAWA
AU - Nozomu TOGAWA
PY - 2015
DO - 10.1587/transfun.E98.A.1376
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2015
AB - In this paper, we first propose an HDR-mcd architecture, which integrates periodically all-in-phase based multiple clock domains and multi-cycle interconnect communication into high-level synthesis. In HDR-mcd, an entire chip is divided into several huddles. Huddles can realize synchronization between different clock domains in which interconnection delay should be considered during high-level synthesis. Next, we propose a high-level synthesis algorithm for HDR-mcd, which can reduce energy consumption by optimizing configuration and placement of huddles. Experimental results show that the proposed method achieves 32.5% energy-saving compared with the existing single clock domain based methods.
ER -
English
