A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs
Summary :
Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.7 pp.1392-1405
- Publication Date
- 2015/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.1392
- Type of Manuscript
- Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
- Category
Authors
Koichi FUJIWARA
Waseda University
Kazushi KAWAMURA
Waseda University
Shin-ya ABE
Waseda University
Masao YANAGISAWA
Waseda University
Nozomu TOGAWA
Waseda University
Keyword
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Koichi FUJIWARA, Kazushi KAWAMURA, Shin-ya ABE, Masao YANAGISAWA, Nozomu TOGAWA, "A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 7, pp. 1392-1405, July 2015, doi: 10.1587/transfun.E98.A.1392.
Abstract: Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.1392/_p
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@ARTICLE{e98-a_7_1392,
author={Koichi FUJIWARA, Kazushi KAWAMURA, Shin-ya ABE, Masao YANAGISAWA, Nozomu TOGAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs},
year={2015},
volume={E98-A},
number={7},
pages={1392-1405},
abstract={Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same.},
keywords={},
doi={10.1587/transfun.E98.A.1392},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1392
EP - 1405
AU - Koichi FUJIWARA
AU - Kazushi KAWAMURA
AU - Shin-ya ABE
AU - Masao YANAGISAWA
AU - Nozomu TOGAWA
PY - 2015
DO - 10.1587/transfun.E98.A.1392
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2015
AB - Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same.
ER -
English
