IEICE TRANSACTIONS on Fundamentals
Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC
Summary :
In this paper, a specified hardware architecture of the Fast Mode Decision (FMD) algorithms presented by our previous work is proposed. This architecture is designed as an embedded mode dispatch module. On the basis of this module, some unnecessary modes can be skipped or the mode decision process can be terminated in advanced. In order to maintain a higher compatibility, the FMD algorithms are unitedly designed as an unique module that can be easily embedded into a common video codec for H.265/HEVC. The input and output interfaces between the proposed module and other parts of the codec are designed based on simple but effective protocol. Hardware synthesis results on FPGA demonstrate that the proposed architecture achieves a maximum frequency of about 193 MHz with less than 1% of the total resources consumed. Moreover, the proposed module can improve the overall throughput.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.8 pp.1787-1795
- Publication Date
- 2015/08/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.1787
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Wenjun ZHAO
Osaka University
Takao ONOYE
Osaka University
Tian SONG
Tokushima University
Keyword
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Wenjun ZHAO, Takao ONOYE, Tian SONG, "Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 8, pp. 1787-1795, August 2015, doi: 10.1587/transfun.E98.A.1787.
Abstract: In this paper, a specified hardware architecture of the Fast Mode Decision (FMD) algorithms presented by our previous work is proposed. This architecture is designed as an embedded mode dispatch module. On the basis of this module, some unnecessary modes can be skipped or the mode decision process can be terminated in advanced. In order to maintain a higher compatibility, the FMD algorithms are unitedly designed as an unique module that can be easily embedded into a common video codec for H.265/HEVC. The input and output interfaces between the proposed module and other parts of the codec are designed based on simple but effective protocol. Hardware synthesis results on FPGA demonstrate that the proposed architecture achieves a maximum frequency of about 193 MHz with less than 1% of the total resources consumed. Moreover, the proposed module can improve the overall throughput.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.1787/_p
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@ARTICLE{e98-a_8_1787,
author={Wenjun ZHAO, Takao ONOYE, Tian SONG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC},
year={2015},
volume={E98-A},
number={8},
pages={1787-1795},
abstract={In this paper, a specified hardware architecture of the Fast Mode Decision (FMD) algorithms presented by our previous work is proposed. This architecture is designed as an embedded mode dispatch module. On the basis of this module, some unnecessary modes can be skipped or the mode decision process can be terminated in advanced. In order to maintain a higher compatibility, the FMD algorithms are unitedly designed as an unique module that can be easily embedded into a common video codec for H.265/HEVC. The input and output interfaces between the proposed module and other parts of the codec are designed based on simple but effective protocol. Hardware synthesis results on FPGA demonstrate that the proposed architecture achieves a maximum frequency of about 193 MHz with less than 1% of the total resources consumed. Moreover, the proposed module can improve the overall throughput.},
keywords={},
doi={10.1587/transfun.E98.A.1787},
ISSN={1745-1337},
month={August},}
Copy
TY - JOUR
TI - Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1787
EP - 1795
AU - Wenjun ZHAO
AU - Takao ONOYE
AU - Tian SONG
PY - 2015
DO - 10.1587/transfun.E98.A.1787
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2015
AB - In this paper, a specified hardware architecture of the Fast Mode Decision (FMD) algorithms presented by our previous work is proposed. This architecture is designed as an embedded mode dispatch module. On the basis of this module, some unnecessary modes can be skipped or the mode decision process can be terminated in advanced. In order to maintain a higher compatibility, the FMD algorithms are unitedly designed as an unique module that can be easily embedded into a common video codec for H.265/HEVC. The input and output interfaces between the proposed module and other parts of the codec are designed based on simple but effective protocol. Hardware synthesis results on FPGA demonstrate that the proposed architecture achieves a maximum frequency of about 193 MHz with less than 1% of the total resources consumed. Moreover, the proposed module can improve the overall throughput.
ER -
English
