High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder

Jianbin ZHOU; Dajiang ZHOU; Shihao WANG; Takeshi YOSHIMURA; Satoshi GOTO

doi:10.1587/transfun.E98.A.2519

IEICE TRANSACTIONS on Fundamentals

High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder

Jianbin ZHOU, Dajiang ZHOU, Shihao WANG, Takeshi YOSHIMURA, Satoshi GOTO

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8K Ultra High Definition Television (UHDTV) requires extremely high throughput for video decoding based on H.265. In H.265, intra coding could significantly enhance video compression efficiency, at the expense of an increased computational complexity compared with H.264. For intra prediction of 8K UHDTV real-time H.265 decoding, the joint complexity and throughput issue is more difficult to solve. Therefore, based on the divide-and-conquer strategy, we propose a new VLSI architecture in this paper, including two techniques, in order to achieve 8K UHDTV H.265 intra prediction decoding. The first technique is the LUT based Reference Sample Fetching Scheme (LUT-RSFS), reducing the number of reference samples in the worst case from 99 to 13. It further reduces the circuit area and enhances the performance. The second one is the Hybrid Block Reordering and Data Forwarding (HBRDF), minimizing the idle time and eliminating the dependency between TUs by creating 3 Data Forwarding paths. It achieves the hardware utilization of 94%. Our design is synthesized using Synopsys Design Compiler in 40nm process technology. It achieves an operation frequency of 260MHz, with a gate count of 217.8K for 8-bit design, and 251.1K for 10-bit design. The proposed VLSI architecture can support 4320p@120fps H.265 intra decoding (8-bit or 10-bit), with all 35 intra prediction modes and prediction unit sizes ranging from 4×4 to 64×64.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.12 pp.2519-2527

Publication Date: 2015/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1587/transfun.E98.A.2519

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: High-Level Synthesis and System-Level Design

Authors

Jianbin ZHOU
  Waseda University
Dajiang ZHOU
  Waseda University
Shihao WANG
  Waseda University
Takeshi YOSHIMURA
  Waseda University
Satoshi GOTO
  Waseda University

Keyword

HEVC/H.265 decoder, intra prediction, VLSI architecture, 8K UHDTV

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Jianbin ZHOU, Dajiang ZHOU, Shihao WANG, Takeshi YOSHIMURA, Satoshi GOTO, "High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder" in IEICE TRANSACTIONS on Fundamentals, vol. E98-A, no. 12, pp. 2519-2527, December 2015, doi: 10.1587/transfun.E98.A.2519.
Abstract: 8K Ultra High Definition Television (UHDTV) requires extremely high throughput for video decoding based on H.265. In H.265, intra coding could significantly enhance video compression efficiency, at the expense of an increased computational complexity compared with H.264. For intra prediction of 8K UHDTV real-time H.265 decoding, the joint complexity and throughput issue is more difficult to solve. Therefore, based on the divide-and-conquer strategy, we propose a new VLSI architecture in this paper, including two techniques, in order to achieve 8K UHDTV H.265 intra prediction decoding. The first technique is the LUT based Reference Sample Fetching Scheme (LUT-RSFS), reducing the number of reference samples in the worst case from 99 to 13. It further reduces the circuit area and enhances the performance. The second one is the Hybrid Block Reordering and Data Forwarding (HBRDF), minimizing the idle time and eliminating the dependency between TUs by creating 3 Data Forwarding paths. It achieves the hardware utilization of 94%. Our design is synthesized using Synopsys Design Compiler in 40nm process technology. It achieves an operation frequency of 260MHz, with a gate count of 217.8K for 8-bit design, and 251.1K for 10-bit design. The proposed VLSI architecture can support 4320p@120fps H.265 intra decoding (8-bit or 10-bit), with all 35 intra prediction modes and prediction unit sizes ranging from 4×4 to 64×64.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.2519/_p

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@ARTICLE{e98-a_12_2519,
author={Jianbin ZHOU, Dajiang ZHOU, Shihao WANG, Takeshi YOSHIMURA, Satoshi GOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder},
year={2015},
volume={E98-A},
number={12},
pages={2519-2527},
abstract={8K Ultra High Definition Television (UHDTV) requires extremely high throughput for video decoding based on H.265. In H.265, intra coding could significantly enhance video compression efficiency, at the expense of an increased computational complexity compared with H.264. For intra prediction of 8K UHDTV real-time H.265 decoding, the joint complexity and throughput issue is more difficult to solve. Therefore, based on the divide-and-conquer strategy, we propose a new VLSI architecture in this paper, including two techniques, in order to achieve 8K UHDTV H.265 intra prediction decoding. The first technique is the LUT based Reference Sample Fetching Scheme (LUT-RSFS), reducing the number of reference samples in the worst case from 99 to 13. It further reduces the circuit area and enhances the performance. The second one is the Hybrid Block Reordering and Data Forwarding (HBRDF), minimizing the idle time and eliminating the dependency between TUs by creating 3 Data Forwarding paths. It achieves the hardware utilization of 94%. Our design is synthesized using Synopsys Design Compiler in 40nm process technology. It achieves an operation frequency of 260MHz, with a gate count of 217.8K for 8-bit design, and 251.1K for 10-bit design. The proposed VLSI architecture can support 4320p@120fps H.265 intra decoding (8-bit or 10-bit), with all 35 intra prediction modes and prediction unit sizes ranging from 4×4 to 64×64.},
keywords={},
doi={10.1587/transfun.E98.A.2519},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - High Performance VLSI Architecture of H.265/HEVC Intra Prediction for 8K UHDTV Video Decoder
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2519
EP - 2527
AU - Jianbin ZHOU
AU - Dajiang ZHOU
AU - Shihao WANG
AU - Takeshi YOSHIMURA
AU - Satoshi GOTO
PY - 2015
DO - 10.1587/transfun.E98.A.2519
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2015
AB - 8K Ultra High Definition Television (UHDTV) requires extremely high throughput for video decoding based on H.265. In H.265, intra coding could significantly enhance video compression efficiency, at the expense of an increased computational complexity compared with H.264. For intra prediction of 8K UHDTV real-time H.265 decoding, the joint complexity and throughput issue is more difficult to solve. Therefore, based on the divide-and-conquer strategy, we propose a new VLSI architecture in this paper, including two techniques, in order to achieve 8K UHDTV H.265 intra prediction decoding. The first technique is the LUT based Reference Sample Fetching Scheme (LUT-RSFS), reducing the number of reference samples in the worst case from 99 to 13. It further reduces the circuit area and enhances the performance. The second one is the Hybrid Block Reordering and Data Forwarding (HBRDF), minimizing the idle time and eliminating the dependency between TUs by creating 3 Data Forwarding paths. It achieves the hardware utilization of 94%. Our design is synthesized using Synopsys Design Compiler in 40nm process technology. It achieves an operation frequency of 260MHz, with a gate count of 217.8K for 8-bit design, and 251.1K for 10-bit design. The proposed VLSI architecture can support 4320p@120fps H.265 intra decoding (8-bit or 10-bit), with all 35 intra prediction modes and prediction unit sizes ranging from 4×4 to 64×64.
ER -

IEICE TRANSACTIONS on Fundamentals