IEICE TRANSACTIONS on Fundamentals
Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators
Summary :
For an FPGA-based heterogeneous multicore platform, we present the design methodology to reduce the total processing time considering data-transfer. The reconfigurability of recent FPGAs with hard CPU cores allows us to realize a single-chip heterogeneous processor optimized for a given application. The major problem in designing such heterogeneous processors is data-transfer between CPU cores and accelerator cores. The total processing time with data-transfers is modeled considering the overlap of computation time and data-transfer time, and optimal design parameters are searched for.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.12 pp.2658-2669
- Publication Date
- 2015/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.2658
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Yasuhiro TAKEI
Tohoku University
Hasitha Muthumala WAIDYASOORIYA
Tohoku University
Masanori HARIYAMA
Tohoku University
Michitaka KAMEYAMA
Tohoku University
Keyword
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Yasuhiro TAKEI, Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA, "Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 12, pp. 2658-2669, December 2015, doi: 10.1587/transfun.E98.A.2658.
Abstract: For an FPGA-based heterogeneous multicore platform, we present the design methodology to reduce the total processing time considering data-transfer. The reconfigurability of recent FPGAs with hard CPU cores allows us to realize a single-chip heterogeneous processor optimized for a given application. The major problem in designing such heterogeneous processors is data-transfer between CPU cores and accelerator cores. The total processing time with data-transfers is modeled considering the overlap of computation time and data-transfer time, and optimal design parameters are searched for.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.2658/_p
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@ARTICLE{e98-a_12_2658,
author={Yasuhiro TAKEI, Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators},
year={2015},
volume={E98-A},
number={12},
pages={2658-2669},
abstract={For an FPGA-based heterogeneous multicore platform, we present the design methodology to reduce the total processing time considering data-transfer. The reconfigurability of recent FPGAs with hard CPU cores allows us to realize a single-chip heterogeneous processor optimized for a given application. The major problem in designing such heterogeneous processors is data-transfer between CPU cores and accelerator cores. The total processing time with data-transfers is modeled considering the overlap of computation time and data-transfer time, and optimal design parameters are searched for.},
keywords={},
doi={10.1587/transfun.E98.A.2658},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2658
EP - 2669
AU - Yasuhiro TAKEI
AU - Hasitha Muthumala WAIDYASOORIYA
AU - Masanori HARIYAMA
AU - Michitaka KAMEYAMA
PY - 2015
DO - 10.1587/transfun.E98.A.2658
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2015
AB - For an FPGA-based heterogeneous multicore platform, we present the design methodology to reduce the total processing time considering data-transfer. The reconfigurability of recent FPGAs with hard CPU cores allows us to realize a single-chip heterogeneous processor optimized for a given application. The major problem in designing such heterogeneous processors is data-transfer between CPU cores and accelerator cores. The total processing time with data-transfers is modeled considering the overlap of computation time and data-transfer time, and optimal design parameters are searched for.
ER -
English
