Efficient Algorithm and Fast Hardware Implementation for Multiply-by-(1+2k)
Summary :
A constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units, and they are prevalent in modern VLSI designs. This study presents an efficient algorithm and fast hardware implementation for performing multiply-by-(1+2k) operation with additions. No multiplications are needed. The value of (1+2k)N can be computed by adding N to its k-bit left-shifted value 2kN. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper introduces the unit cells for additions (UCAs) to construct the UCA-based RCA which achieves 35% faster than the FA-based RCA in speed performance. Further, in order to improve the speed performance, a simple and modular hybrid adder is presented with the proposed UCA concept, where the carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the hybrid adder significantly improves the speed performance.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.4 pp.966-974
- Publication Date
- 2015/04/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.966
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
Authors
Chin-Long WEY
National Chiao Tung University
Ping-Chang JUI
National Central University
Muh-Tian SHIUE
National Central University
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Chin-Long WEY, Ping-Chang JUI, Muh-Tian SHIUE, "Efficient Algorithm and Fast Hardware Implementation for Multiply-by-(1+2k)" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 4, pp. 966-974, April 2015, doi: 10.1587/transfun.E98.A.966.
Abstract: A constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units, and they are prevalent in modern VLSI designs. This study presents an efficient algorithm and fast hardware implementation for performing multiply-by-(1+2k) operation with additions. No multiplications are needed. The value of (1+2k)N can be computed by adding N to its k-bit left-shifted value 2kN. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper introduces the unit cells for additions (UCAs) to construct the UCA-based RCA which achieves 35% faster than the FA-based RCA in speed performance. Further, in order to improve the speed performance, a simple and modular hybrid adder is presented with the proposed UCA concept, where the carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the hybrid adder significantly improves the speed performance.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.966/_p
Copy
@ARTICLE{e98-a_4_966,
author={Chin-Long WEY, Ping-Chang JUI, Muh-Tian SHIUE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Efficient Algorithm and Fast Hardware Implementation for Multiply-by-(1+2k)},
year={2015},
volume={E98-A},
number={4},
pages={966-974},
abstract={A constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units, and they are prevalent in modern VLSI designs. This study presents an efficient algorithm and fast hardware implementation for performing multiply-by-(1+2k) operation with additions. No multiplications are needed. The value of (1+2k)N can be computed by adding N to its k-bit left-shifted value 2kN. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper introduces the unit cells for additions (UCAs) to construct the UCA-based RCA which achieves 35% faster than the FA-based RCA in speed performance. Further, in order to improve the speed performance, a simple and modular hybrid adder is presented with the proposed UCA concept, where the carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the hybrid adder significantly improves the speed performance.},
keywords={},
doi={10.1587/transfun.E98.A.966},
ISSN={1745-1337},
month={April},}
Copy
TY - JOUR
TI - Efficient Algorithm and Fast Hardware Implementation for Multiply-by-(1+2k)
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 966
EP - 974
AU - Chin-Long WEY
AU - Ping-Chang JUI
AU - Muh-Tian SHIUE
PY - 2015
DO - 10.1587/transfun.E98.A.966
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2015
AB - A constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units, and they are prevalent in modern VLSI designs. This study presents an efficient algorithm and fast hardware implementation for performing multiply-by-(1+2k) operation with additions. No multiplications are needed. The value of (1+2k)N can be computed by adding N to its k-bit left-shifted value 2kN. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper introduces the unit cells for additions (UCAs) to construct the UCA-based RCA which achieves 35% faster than the FA-based RCA in speed performance. Further, in order to improve the speed performance, a simple and modular hybrid adder is presented with the proposed UCA concept, where the carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the hybrid adder significantly improves the speed performance.
ER -
English
