IEICE TRANSACTIONS on Fundamentals
Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing
Summary :
As semiconductor technologies have advanced, the reliability problem caused by soft-errors is becoming one of the serious issues in LSIs. Moreover, multiple component errors due to single soft-errors also have become a serious problem. In this paper, we propose a method to synthesize multiple component soft-error tolerant application-specific datapaths via high-level synthesis. The novel feature of our method is speculative resource sharing between the retry parts and the secondary parts for time overhead mitigation. A scheduling algorithm using a special priority function to maximize speculative resource sharing is also an important feature of this study. Our approach can reduce the latency (schedule length) in many applications without deterioration of reliability and chip area compared with conventional datapaths without speculative resource sharing. We also found that our method is more effective when a computation algorithm possesses higher parallelism and a smaller number of resources is available.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.7 pp.1311-1322
- Publication Date
- 2016/07/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E99.A.1311
- Type of Manuscript
- Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
- Category
Authors
Junghoon OH
Japan Advanced Institute of Science and Technology
Mineo KANEKO
Japan Advanced Institute of Science and Technology
Keyword
Latest Issue
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Junghoon OH, Mineo KANEKO, "Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing" in IEICE TRANSACTIONS on Fundamentals,
vol. E99-A, no. 7, pp. 1311-1322, July 2016, doi: 10.1587/transfun.E99.A.1311.
Abstract: As semiconductor technologies have advanced, the reliability problem caused by soft-errors is becoming one of the serious issues in LSIs. Moreover, multiple component errors due to single soft-errors also have become a serious problem. In this paper, we propose a method to synthesize multiple component soft-error tolerant application-specific datapaths via high-level synthesis. The novel feature of our method is speculative resource sharing between the retry parts and the secondary parts for time overhead mitigation. A scheduling algorithm using a special priority function to maximize speculative resource sharing is also an important feature of this study. Our approach can reduce the latency (schedule length) in many applications without deterioration of reliability and chip area compared with conventional datapaths without speculative resource sharing. We also found that our method is more effective when a computation algorithm possesses higher parallelism and a smaller number of resources is available.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.1311/_p
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@ARTICLE{e99-a_7_1311,
author={Junghoon OH, Mineo KANEKO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing},
year={2016},
volume={E99-A},
number={7},
pages={1311-1322},
abstract={As semiconductor technologies have advanced, the reliability problem caused by soft-errors is becoming one of the serious issues in LSIs. Moreover, multiple component errors due to single soft-errors also have become a serious problem. In this paper, we propose a method to synthesize multiple component soft-error tolerant application-specific datapaths via high-level synthesis. The novel feature of our method is speculative resource sharing between the retry parts and the secondary parts for time overhead mitigation. A scheduling algorithm using a special priority function to maximize speculative resource sharing is also an important feature of this study. Our approach can reduce the latency (schedule length) in many applications without deterioration of reliability and chip area compared with conventional datapaths without speculative resource sharing. We also found that our method is more effective when a computation algorithm possesses higher parallelism and a smaller number of resources is available.},
keywords={},
doi={10.1587/transfun.E99.A.1311},
ISSN={1745-1337},
month={July},}
Copy
TY - JOUR
TI - Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1311
EP - 1322
AU - Junghoon OH
AU - Mineo KANEKO
PY - 2016
DO - 10.1587/transfun.E99.A.1311
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2016
AB - As semiconductor technologies have advanced, the reliability problem caused by soft-errors is becoming one of the serious issues in LSIs. Moreover, multiple component errors due to single soft-errors also have become a serious problem. In this paper, we propose a method to synthesize multiple component soft-error tolerant application-specific datapaths via high-level synthesis. The novel feature of our method is speculative resource sharing between the retry parts and the secondary parts for time overhead mitigation. A scheduling algorithm using a special priority function to maximize speculative resource sharing is also an important feature of this study. Our approach can reduce the latency (schedule length) in many applications without deterioration of reliability and chip area compared with conventional datapaths without speculative resource sharing. We also found that our method is more effective when a computation algorithm possesses higher parallelism and a smaller number of resources is available.
ER -
English
