As the semiconductor technology continues to develop, hundreds of cores will be deployed on a single die in the future Chip-Multiprocessors (CMPs) design. Three-Dimensional Network-on-Chips (3D NoCs) has become an attractive solution which can provide impressive high performance. An efficient and deadlock-free routing algorithm is a critical to achieve the high performance of network-on-chip. Traditional methods based on deterministic and turn model are deadlock-free, but they are unable to distribute the traffic loads over the network. In this paper, we propose an efficient, adaptive and deadlock-free algorithm (EAR) based on a novel routing selection strategy in 3D NoC, which can distribute the traffic loads not only in intra-layers but also in inter-layers according to congestion information and path diversity. Simulation results show that the proposed method achieves the significant performance improvement compared with others.
Lian ZENG
Waseda University
Tieyuan PAN
Waseda University
Xin JIANG
Waseda University
Takahiro WATANABE
Waseda University
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Lian ZENG, Tieyuan PAN, Xin JIANG, Takahiro WATANABE, "An Efficient Highly Adaptive and Deadlock-Free Routing Algorithm for 3D Network-on-Chip" in IEICE TRANSACTIONS on Fundamentals,
vol. E99-A, no. 7, pp. 1334-1344, July 2016, doi: 10.1587/transfun.E99.A.1334.
Abstract: As the semiconductor technology continues to develop, hundreds of cores will be deployed on a single die in the future Chip-Multiprocessors (CMPs) design. Three-Dimensional Network-on-Chips (3D NoCs) has become an attractive solution which can provide impressive high performance. An efficient and deadlock-free routing algorithm is a critical to achieve the high performance of network-on-chip. Traditional methods based on deterministic and turn model are deadlock-free, but they are unable to distribute the traffic loads over the network. In this paper, we propose an efficient, adaptive and deadlock-free algorithm (EAR) based on a novel routing selection strategy in 3D NoC, which can distribute the traffic loads not only in intra-layers but also in inter-layers according to congestion information and path diversity. Simulation results show that the proposed method achieves the significant performance improvement compared with others.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.1334/_p
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@ARTICLE{e99-a_7_1334,
author={Lian ZENG, Tieyuan PAN, Xin JIANG, Takahiro WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Efficient Highly Adaptive and Deadlock-Free Routing Algorithm for 3D Network-on-Chip},
year={2016},
volume={E99-A},
number={7},
pages={1334-1344},
abstract={As the semiconductor technology continues to develop, hundreds of cores will be deployed on a single die in the future Chip-Multiprocessors (CMPs) design. Three-Dimensional Network-on-Chips (3D NoCs) has become an attractive solution which can provide impressive high performance. An efficient and deadlock-free routing algorithm is a critical to achieve the high performance of network-on-chip. Traditional methods based on deterministic and turn model are deadlock-free, but they are unable to distribute the traffic loads over the network. In this paper, we propose an efficient, adaptive and deadlock-free algorithm (EAR) based on a novel routing selection strategy in 3D NoC, which can distribute the traffic loads not only in intra-layers but also in inter-layers according to congestion information and path diversity. Simulation results show that the proposed method achieves the significant performance improvement compared with others.},
keywords={},
doi={10.1587/transfun.E99.A.1334},
ISSN={1745-1337},
month={July},}
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TY - JOUR
TI - An Efficient Highly Adaptive and Deadlock-Free Routing Algorithm for 3D Network-on-Chip
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1334
EP - 1344
AU - Lian ZENG
AU - Tieyuan PAN
AU - Xin JIANG
AU - Takahiro WATANABE
PY - 2016
DO - 10.1587/transfun.E99.A.1334
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2016
AB - As the semiconductor technology continues to develop, hundreds of cores will be deployed on a single die in the future Chip-Multiprocessors (CMPs) design. Three-Dimensional Network-on-Chips (3D NoCs) has become an attractive solution which can provide impressive high performance. An efficient and deadlock-free routing algorithm is a critical to achieve the high performance of network-on-chip. Traditional methods based on deterministic and turn model are deadlock-free, but they are unable to distribute the traffic loads over the network. In this paper, we propose an efficient, adaptive and deadlock-free algorithm (EAR) based on a novel routing selection strategy in 3D NoC, which can distribute the traffic loads not only in intra-layers but also in inter-layers according to congestion information and path diversity. Simulation results show that the proposed method achieves the significant performance improvement compared with others.
ER -