Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration
Summary :
SUMMARY This paper proposes a power-supply-noise-aware timing analysis and test pattern regeneration framework suitable for testing 3D IC. The proposed framework analyzes timing with reasonable accuracy at much faster speed than existing tools. This technique is very scalable because it is based on analytical functions, instead of solving nonlinear equations. The experimental results show, for small circuits, the error is less than 2% compared with SPICE. For large circuits, we achieved 272 times speed up compared with a commercial tool. For a large benchmark circuit (638K gates), we identified 88 risky patterns out of 31K test patterns. We propose a test pattern regeneration flow to replace those risky patterns with very little (or even no) penalty in fault coverage. Our test sets are shorter than commercial power-aware ATPG while the fault coverage is almost the same as power-unaware ATPG.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.12 pp.2320-2327
- Publication Date
- 2016/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E99.A.2320
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Cheng-Yu HAN
NTU
Yu-Ching LI
NTU
Hao-Tien KAN
NTU
James Chien-Mo LI
NTU
Keyword
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Cheng-Yu HAN, Yu-Ching LI, Hao-Tien KAN, James Chien-Mo LI, "Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration" in IEICE TRANSACTIONS on Fundamentals,
vol. E99-A, no. 12, pp. 2320-2327, December 2016, doi: 10.1587/transfun.E99.A.2320.
Abstract: SUMMARY This paper proposes a power-supply-noise-aware timing analysis and test pattern regeneration framework suitable for testing 3D IC. The proposed framework analyzes timing with reasonable accuracy at much faster speed than existing tools. This technique is very scalable because it is based on analytical functions, instead of solving nonlinear equations. The experimental results show, for small circuits, the error is less than 2% compared with SPICE. For large circuits, we achieved 272 times speed up compared with a commercial tool. For a large benchmark circuit (638K gates), we identified 88 risky patterns out of 31K test patterns. We propose a test pattern regeneration flow to replace those risky patterns with very little (or even no) penalty in fault coverage. Our test sets are shorter than commercial power-aware ATPG while the fault coverage is almost the same as power-unaware ATPG.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.2320/_p
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@ARTICLE{e99-a_12_2320,
author={Cheng-Yu HAN, Yu-Ching LI, Hao-Tien KAN, James Chien-Mo LI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration},
year={2016},
volume={E99-A},
number={12},
pages={2320-2327},
abstract={SUMMARY This paper proposes a power-supply-noise-aware timing analysis and test pattern regeneration framework suitable for testing 3D IC. The proposed framework analyzes timing with reasonable accuracy at much faster speed than existing tools. This technique is very scalable because it is based on analytical functions, instead of solving nonlinear equations. The experimental results show, for small circuits, the error is less than 2% compared with SPICE. For large circuits, we achieved 272 times speed up compared with a commercial tool. For a large benchmark circuit (638K gates), we identified 88 risky patterns out of 31K test patterns. We propose a test pattern regeneration flow to replace those risky patterns with very little (or even no) penalty in fault coverage. Our test sets are shorter than commercial power-aware ATPG while the fault coverage is almost the same as power-unaware ATPG.},
keywords={},
doi={10.1587/transfun.E99.A.2320},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2320
EP - 2327
AU - Cheng-Yu HAN
AU - Yu-Ching LI
AU - Hao-Tien KAN
AU - James Chien-Mo LI
PY - 2016
DO - 10.1587/transfun.E99.A.2320
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2016
AB - SUMMARY This paper proposes a power-supply-noise-aware timing analysis and test pattern regeneration framework suitable for testing 3D IC. The proposed framework analyzes timing with reasonable accuracy at much faster speed than existing tools. This technique is very scalable because it is based on analytical functions, instead of solving nonlinear equations. The experimental results show, for small circuits, the error is less than 2% compared with SPICE. For large circuits, we achieved 272 times speed up compared with a commercial tool. For a large benchmark circuit (638K gates), we identified 88 risky patterns out of 31K test patterns. We propose a test pattern regeneration flow to replace those risky patterns with very little (or even no) penalty in fault coverage. Our test sets are shorter than commercial power-aware ATPG while the fault coverage is almost the same as power-unaware ATPG.
ER -
English
