IEICE TRANSACTIONS on Fundamentals
Low Complexity Reed-Solomon Decoder Design with Pipelined Recursive Euclidean Algorithm
Summary :
A Reed-Solomon (RS) decoder is designed based on the pipelined recursive Euclidean algorithm in the key equation solution. While the Euclidean algorithm uses less Galois multipliers than the modified Euclidean (ME) and reformulated inversionless Berlekamp-Massey (RiBM) algorithms, division between two elements in Galois field is required. By implementing the division with a multi-cycle Galois inverter and a serial Galois multiplier, the proposed key equation solver architecture achieves lower complexity than the conventional ME and RiBM based architectures. The proposed RS (255,239) decoder reduces the hardware complexity by 25.9% with 6.5% increase in decoding latency.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.12 pp.2453-2462
- Publication Date
- 2016/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E99.A.2453
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Kazuhito ITO
Saitama University
Keyword
Latest Issue
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Kazuhito ITO, "Low Complexity Reed-Solomon Decoder Design with Pipelined Recursive Euclidean Algorithm" in IEICE TRANSACTIONS on Fundamentals,
vol. E99-A, no. 12, pp. 2453-2462, December 2016, doi: 10.1587/transfun.E99.A.2453.
Abstract: A Reed-Solomon (RS) decoder is designed based on the pipelined recursive Euclidean algorithm in the key equation solution. While the Euclidean algorithm uses less Galois multipliers than the modified Euclidean (ME) and reformulated inversionless Berlekamp-Massey (RiBM) algorithms, division between two elements in Galois field is required. By implementing the division with a multi-cycle Galois inverter and a serial Galois multiplier, the proposed key equation solver architecture achieves lower complexity than the conventional ME and RiBM based architectures. The proposed RS (255,239) decoder reduces the hardware complexity by 25.9% with 6.5% increase in decoding latency.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.2453/_p
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@ARTICLE{e99-a_12_2453,
author={Kazuhito ITO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Low Complexity Reed-Solomon Decoder Design with Pipelined Recursive Euclidean Algorithm},
year={2016},
volume={E99-A},
number={12},
pages={2453-2462},
abstract={A Reed-Solomon (RS) decoder is designed based on the pipelined recursive Euclidean algorithm in the key equation solution. While the Euclidean algorithm uses less Galois multipliers than the modified Euclidean (ME) and reformulated inversionless Berlekamp-Massey (RiBM) algorithms, division between two elements in Galois field is required. By implementing the division with a multi-cycle Galois inverter and a serial Galois multiplier, the proposed key equation solver architecture achieves lower complexity than the conventional ME and RiBM based architectures. The proposed RS (255,239) decoder reduces the hardware complexity by 25.9% with 6.5% increase in decoding latency.},
keywords={},
doi={10.1587/transfun.E99.A.2453},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Low Complexity Reed-Solomon Decoder Design with Pipelined Recursive Euclidean Algorithm
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2453
EP - 2462
AU - Kazuhito ITO
PY - 2016
DO - 10.1587/transfun.E99.A.2453
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2016
AB - A Reed-Solomon (RS) decoder is designed based on the pipelined recursive Euclidean algorithm in the key equation solution. While the Euclidean algorithm uses less Galois multipliers than the modified Euclidean (ME) and reformulated inversionless Berlekamp-Massey (RiBM) algorithms, division between two elements in Galois field is required. By implementing the division with a multi-cycle Galois inverter and a serial Galois multiplier, the proposed key equation solver architecture achieves lower complexity than the conventional ME and RiBM based architectures. The proposed RS (255,239) decoder reduces the hardware complexity by 25.9% with 6.5% increase in decoding latency.
ER -
English
