IEICE TRANSACTIONS on Fundamentals
SLM: A Scalable Logic Module Architecture with Less Configuration Memory
Summary :
Most modern field programmable gate arrays (FPGAs) use a lookup table (LUT) as their basic logic cell. LUT resource requirements increase as O(2k) with an increasing number of inputs, k, so LUTs with more than six inputs negatively affect the overall FPGA performance. To address this problem, we propose a scalable logic module (SLM), which is a logic cell with less configuration memory, by using partial functions of the Shannon expansion for logics that appear frequently. In addition, we develop a technology mapping tool for SLM. The key feature of our tool is to combine a function decomposition process with traditional cut-based mapping. Experimental results show that an SLM-based FPGA with our mapping method uses much fewer configuration memory bits and has a smaller area than conventional LUT-based FPGAs.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.12 pp.2500-2506
- Publication Date
- 2016/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E99.A.2500
- Type of Manuscript
- Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
- Category
Authors
Motoki AMAGASAKI
Kumamoto University
Ryo ARAKI
Kumamoto University
Masahiro IIDA
Kumamoto University
Toshinori SUEYOSHI
Kumamoto University
Keyword
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Motoki AMAGASAKI, Ryo ARAKI, Masahiro IIDA, Toshinori SUEYOSHI, "SLM: A Scalable Logic Module Architecture with Less Configuration Memory" in IEICE TRANSACTIONS on Fundamentals,
vol. E99-A, no. 12, pp. 2500-2506, December 2016, doi: 10.1587/transfun.E99.A.2500.
Abstract: Most modern field programmable gate arrays (FPGAs) use a lookup table (LUT) as their basic logic cell. LUT resource requirements increase as O(2k) with an increasing number of inputs, k, so LUTs with more than six inputs negatively affect the overall FPGA performance. To address this problem, we propose a scalable logic module (SLM), which is a logic cell with less configuration memory, by using partial functions of the Shannon expansion for logics that appear frequently. In addition, we develop a technology mapping tool for SLM. The key feature of our tool is to combine a function decomposition process with traditional cut-based mapping. Experimental results show that an SLM-based FPGA with our mapping method uses much fewer configuration memory bits and has a smaller area than conventional LUT-based FPGAs.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.2500/_p
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@ARTICLE{e99-a_12_2500,
author={Motoki AMAGASAKI, Ryo ARAKI, Masahiro IIDA, Toshinori SUEYOSHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={SLM: A Scalable Logic Module Architecture with Less Configuration Memory},
year={2016},
volume={E99-A},
number={12},
pages={2500-2506},
abstract={Most modern field programmable gate arrays (FPGAs) use a lookup table (LUT) as their basic logic cell. LUT resource requirements increase as O(2k) with an increasing number of inputs, k, so LUTs with more than six inputs negatively affect the overall FPGA performance. To address this problem, we propose a scalable logic module (SLM), which is a logic cell with less configuration memory, by using partial functions of the Shannon expansion for logics that appear frequently. In addition, we develop a technology mapping tool for SLM. The key feature of our tool is to combine a function decomposition process with traditional cut-based mapping. Experimental results show that an SLM-based FPGA with our mapping method uses much fewer configuration memory bits and has a smaller area than conventional LUT-based FPGAs.},
keywords={},
doi={10.1587/transfun.E99.A.2500},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - SLM: A Scalable Logic Module Architecture with Less Configuration Memory
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2500
EP - 2506
AU - Motoki AMAGASAKI
AU - Ryo ARAKI
AU - Masahiro IIDA
AU - Toshinori SUEYOSHI
PY - 2016
DO - 10.1587/transfun.E99.A.2500
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2016
AB - Most modern field programmable gate arrays (FPGAs) use a lookup table (LUT) as their basic logic cell. LUT resource requirements increase as O(2k) with an increasing number of inputs, k, so LUTs with more than six inputs negatively affect the overall FPGA performance. To address this problem, we propose a scalable logic module (SLM), which is a logic cell with less configuration memory, by using partial functions of the Shannon expansion for logics that appear frequently. In addition, we develop a technology mapping tool for SLM. The key feature of our tool is to combine a function decomposition process with traditional cut-based mapping. Experimental results show that an SLM-based FPGA with our mapping method uses much fewer configuration memory bits and has a smaller area than conventional LUT-based FPGAs.
ER -
English
