0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell

Khaja Ahmad SHAIK; Kiyoo ITOH; Amara AMARA

doi:10.1587/transfun.E99.A.523

0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell

Khaja Ahmad SHAIK, Kiyoo ITOH, Amara AMARA

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To achieve low-voltage low-power SRAMs, two proposals are demonstrated. One is a multi-power-supply five-transistor cell (5T cell), assisted by a boosted word-line voltage and a mid-point sensing enabled by precharging bit-lines to V_DD/2. The cell enables to reduce V_DD to 0.5V or less for a given speed, or enhance speed for a given V_DD. The other is a partial activation of a compact multi-divided open-bit-line array for low power. Layout and post-layout simulation with a 28-nm fully-depleted planar-logic SOI MOSFET reveal that a 0.5-V 5T-cell 4-kb array in a 128-kb SRAM core using the proposals is able to achieve x2-3 faster cycle time and x11 lower power than the counterpart 6T-cell array, suggesting a possibility of a 730-ps cycle time at 0.5V.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E99-A No.2 pp.523-530

Publication Date: 2016/02/01

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Online ISSN: 1745-1337

DOI: 10.1587/transfun.E99.A.523

Type of Manuscript: Special Section INVITED PAPER (Special Section on Analog Circuit Techniques and Related Topics)

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Authors

Khaja Ahmad SHAIK
  Institut supérieur d'électronique de Paris (ISEP)
Kiyoo ITOH
  Institut supérieur d'électronique de Paris (ISEP)
Amara AMARA
  Institut supérieur d'électronique de Paris (ISEP)

Keyword

0.5-V 5T-cell SRAM array, multi-divided open bit-lines, boosted word-line, mid-point sensing

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Khaja Ahmad SHAIK, Kiyoo ITOH, Amara AMARA, "0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell" in IEICE TRANSACTIONS on Fundamentals, vol. E99-A, no. 2, pp. 523-530, February 2016, doi: 10.1587/transfun.E99.A.523.
Abstract: To achieve low-voltage low-power SRAMs, two proposals are demonstrated. One is a multi-power-supply five-transistor cell (5T cell), assisted by a boosted word-line voltage and a mid-point sensing enabled by precharging bit-lines to V_DD/2. The cell enables to reduce V_DD to 0.5V or less for a given speed, or enhance speed for a given V_DD. The other is a partial activation of a compact multi-divided open-bit-line array for low power. Layout and post-layout simulation with a 28-nm fully-depleted planar-logic SOI MOSFET reveal that a 0.5-V 5T-cell 4-kb array in a 128-kb SRAM core using the proposals is able to achieve x2-3 faster cycle time and x11 lower power than the counterpart 6T-cell array, suggesting a possibility of a 730-ps cycle time at 0.5V.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E99.A.523/_p

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@ARTICLE{e99-a_2_523,
author={Khaja Ahmad SHAIK, Kiyoo ITOH, Amara AMARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell},
year={2016},
volume={E99-A},
number={2},
pages={523-530},
abstract={To achieve low-voltage low-power SRAMs, two proposals are demonstrated. One is a multi-power-supply five-transistor cell (5T cell), assisted by a boosted word-line voltage and a mid-point sensing enabled by precharging bit-lines to V_DD/2. The cell enables to reduce V_DD to 0.5V or less for a given speed, or enhance speed for a given V_DD. The other is a partial activation of a compact multi-divided open-bit-line array for low power. Layout and post-layout simulation with a 28-nm fully-depleted planar-logic SOI MOSFET reveal that a 0.5-V 5T-cell 4-kb array in a 128-kb SRAM core using the proposals is able to achieve x2-3 faster cycle time and x11 lower power than the counterpart 6T-cell array, suggesting a possibility of a 730-ps cycle time at 0.5V.},
keywords={},
doi={10.1587/transfun.E99.A.523},
ISSN={1745-1337},
month={February},}

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TY - JOUR
TI - 0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 523
EP - 530
AU - Khaja Ahmad SHAIK
AU - Kiyoo ITOH
AU - Amara AMARA
PY - 2016
DO - 10.1587/transfun.E99.A.523
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E99-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2016
AB - To achieve low-voltage low-power SRAMs, two proposals are demonstrated. One is a multi-power-supply five-transistor cell (5T cell), assisted by a boosted word-line voltage and a mid-point sensing enabled by precharging bit-lines to V_DD/2. The cell enables to reduce V_DD to 0.5V or less for a given speed, or enhance speed for a given V_DD. The other is a partial activation of a compact multi-divided open-bit-line array for low power. Layout and post-layout simulation with a 28-nm fully-depleted planar-logic SOI MOSFET reveal that a 0.5-V 5T-cell 4-kb array in a 128-kb SRAM core using the proposals is able to achieve x2-3 faster cycle time and x11 lower power than the counterpart 6T-cell array, suggesting a possibility of a 730-ps cycle time at 0.5V.
ER -