IEICE TRANSACTIONS on Information
Speculative Branch Folding for Pipelined Processors
Summary :
This paper proposes an effective branch folding technique which combines branch instructions with predicted instructions. This technique can be implemented using an instruction queue, which buffers prefetched instructions. Most of the instructions in the instruction queue are forwarded to the execution unit in sequence. Branch instructions, however, are combined with predicted instructions in the instruction queue and these folded instructions are forwarded to the execution unit. Miss-prediction can be recovered by flushing folded instructions without processor state recovery and by restarting from the other path. Simulation and implementation results show that both performance and power consumption are significantly improved with little additional hardware cost.
- Publication
- IEICE TRANSACTIONS on Information Vol.E88-D No.5 pp.1064-1066
- Publication Date
- 2005/05/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietisy/e88-d.5.1064
- Type of Manuscript
- LETTER
- Category
- Computer Systems
Authors
Keyword
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Sang-Hyun PARK, Sungwook YU, Jung-Wan CHO, "Speculative Branch Folding for Pipelined Processors" in IEICE TRANSACTIONS on Information,
vol. E88-D, no. 5, pp. 1064-1066, May 2005, doi: 10.1093/ietisy/e88-d.5.1064.
Abstract: This paper proposes an effective branch folding technique which combines branch instructions with predicted instructions. This technique can be implemented using an instruction queue, which buffers prefetched instructions. Most of the instructions in the instruction queue are forwarded to the execution unit in sequence. Branch instructions, however, are combined with predicted instructions in the instruction queue and these folded instructions are forwarded to the execution unit. Miss-prediction can be recovered by flushing folded instructions without processor state recovery and by restarting from the other path. Simulation and implementation results show that both performance and power consumption are significantly improved with little additional hardware cost.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.5.1064/_p
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@ARTICLE{e88-d_5_1064,
author={Sang-Hyun PARK, Sungwook YU, Jung-Wan CHO, },
journal={IEICE TRANSACTIONS on Information},
title={Speculative Branch Folding for Pipelined Processors},
year={2005},
volume={E88-D},
number={5},
pages={1064-1066},
abstract={This paper proposes an effective branch folding technique which combines branch instructions with predicted instructions. This technique can be implemented using an instruction queue, which buffers prefetched instructions. Most of the instructions in the instruction queue are forwarded to the execution unit in sequence. Branch instructions, however, are combined with predicted instructions in the instruction queue and these folded instructions are forwarded to the execution unit. Miss-prediction can be recovered by flushing folded instructions without processor state recovery and by restarting from the other path. Simulation and implementation results show that both performance and power consumption are significantly improved with little additional hardware cost.},
keywords={},
doi={10.1093/ietisy/e88-d.5.1064},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - Speculative Branch Folding for Pipelined Processors
T2 - IEICE TRANSACTIONS on Information
SP - 1064
EP - 1066
AU - Sang-Hyun PARK
AU - Sungwook YU
AU - Jung-Wan CHO
PY - 2005
DO - 10.1093/ietisy/e88-d.5.1064
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2005
AB - This paper proposes an effective branch folding technique which combines branch instructions with predicted instructions. This technique can be implemented using an instruction queue, which buffers prefetched instructions. Most of the instructions in the instruction queue are forwarded to the execution unit in sequence. Branch instructions, however, are combined with predicted instructions in the instruction queue and these folded instructions are forwarded to the execution unit. Miss-prediction can be recovered by flushing folded instructions without processor state recovery and by restarting from the other path. Simulation and implementation results show that both performance and power consumption are significantly improved with little additional hardware cost.
ER -
English
