Boundary Scan Test Scheme for IP Core Identification via Watermarking
Summary :
This paper proposes a novel boundary scan test scheme for intellectual property (IP) core identification via watermarking. The core concept is embedding a watermark identification circuit (WIC) and a test circuit into the IP core at the behavior design level. The procedure depends on current IP-based design flow. This scheme can detect the identification of the IP provider without the need to examine the microphotograph after the chip has been manufactured and packaged. This scheme can successfully survive synthesis, placement, and routing and identify the IP core at various design levels. Experimental results have demonstrated that the proposed approach has the potential to solve the IP identification problem.
- Publication
- IEICE TRANSACTIONS on Information Vol.E88-D No.7 pp.1397-1400
- Publication Date
- 2005/07/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietisy/e88-d.7.1397
- Type of Manuscript
- Special Section LETTER (Special Section on Recent Advances in Circuits and Systems--Part 1)
- Category
- Programmable Logic, VLSI, CAD and Layout
Authors
Keyword
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Yu-Cheng FAN, Hen-Wai TSAO, "Boundary Scan Test Scheme for IP Core Identification via Watermarking" in IEICE TRANSACTIONS on Information,
vol. E88-D, no. 7, pp. 1397-1400, July 2005, doi: 10.1093/ietisy/e88-d.7.1397.
Abstract: This paper proposes a novel boundary scan test scheme for intellectual property (IP) core identification via watermarking. The core concept is embedding a watermark identification circuit (WIC) and a test circuit into the IP core at the behavior design level. The procedure depends on current IP-based design flow. This scheme can detect the identification of the IP provider without the need to examine the microphotograph after the chip has been manufactured and packaged. This scheme can successfully survive synthesis, placement, and routing and identify the IP core at various design levels. Experimental results have demonstrated that the proposed approach has the potential to solve the IP identification problem.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.7.1397/_p
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@ARTICLE{e88-d_7_1397,
author={Yu-Cheng FAN, Hen-Wai TSAO, },
journal={IEICE TRANSACTIONS on Information},
title={Boundary Scan Test Scheme for IP Core Identification via Watermarking},
year={2005},
volume={E88-D},
number={7},
pages={1397-1400},
abstract={This paper proposes a novel boundary scan test scheme for intellectual property (IP) core identification via watermarking. The core concept is embedding a watermark identification circuit (WIC) and a test circuit into the IP core at the behavior design level. The procedure depends on current IP-based design flow. This scheme can detect the identification of the IP provider without the need to examine the microphotograph after the chip has been manufactured and packaged. This scheme can successfully survive synthesis, placement, and routing and identify the IP core at various design levels. Experimental results have demonstrated that the proposed approach has the potential to solve the IP identification problem.},
keywords={},
doi={10.1093/ietisy/e88-d.7.1397},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - Boundary Scan Test Scheme for IP Core Identification via Watermarking
T2 - IEICE TRANSACTIONS on Information
SP - 1397
EP - 1400
AU - Yu-Cheng FAN
AU - Hen-Wai TSAO
PY - 2005
DO - 10.1093/ietisy/e88-d.7.1397
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2005
AB - This paper proposes a novel boundary scan test scheme for intellectual property (IP) core identification via watermarking. The core concept is embedding a watermark identification circuit (WIC) and a test circuit into the IP core at the behavior design level. The procedure depends on current IP-based design flow. This scheme can detect the identification of the IP provider without the need to examine the microphotograph after the chip has been manufactured and packaged. This scheme can successfully survive synthesis, placement, and routing and identify the IP core at various design levels. Experimental results have demonstrated that the proposed approach has the potential to solve the IP identification problem.
ER -
English
