IEICE TRANSACTIONS on Information
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access
Summary :
This paper presents a VLSI processor for high-speed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.
- Publication
- IEICE TRANSACTIONS on Information Vol.E88-D No.7 pp.1486-1491
- Publication Date
- 2005/07/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietisy/e88-d.7.1486
- Type of Manuscript
- Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
- Category
- Digital Circuits and Computer Arithmetic
Authors
Keyword
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Masanori HARIYAMA, Haruka SASAKI, Michitaka KAMEYAMA, "Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access" in IEICE TRANSACTIONS on Information,
vol. E88-D, no. 7, pp. 1486-1491, July 2005, doi: 10.1093/ietisy/e88-d.7.1486.
Abstract: This paper presents a VLSI processor for high-speed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.7.1486/_p
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@ARTICLE{e88-d_7_1486,
author={Masanori HARIYAMA, Haruka SASAKI, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Information},
title={Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access},
year={2005},
volume={E88-D},
number={7},
pages={1486-1491},
abstract={This paper presents a VLSI processor for high-speed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.},
keywords={},
doi={10.1093/ietisy/e88-d.7.1486},
ISSN={},
month={July},}
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TY - JOUR
TI - Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access
T2 - IEICE TRANSACTIONS on Information
SP - 1486
EP - 1491
AU - Masanori HARIYAMA
AU - Haruka SASAKI
AU - Michitaka KAMEYAMA
PY - 2005
DO - 10.1093/ietisy/e88-d.7.1486
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2005
AB - This paper presents a VLSI processor for high-speed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi-resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.
ER -
English
