IEICE TRANSACTIONS on Information
Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders
Summary :
This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EX-SOPs where some outputs of the function are minimized in the complemented form and presented techniques to minimize EX-SOPs for adders by using an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. The proposed algorithm produces solutions with a half products of AOXMIN-like algorithm in 250 times shorter time for large adders with two-valued inputs. We also proved that an n-bit adder with two-valued inputs requires at most 3
- Publication
- IEICE TRANSACTIONS on Information Vol.E88-D No.7 pp.1492-1500
- Publication Date
- 2005/07/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietisy/e88-d.7.1492
- Type of Manuscript
- Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
- Category
- Digital Circuits and Computer Arithmetic
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Debatosh DEBNATH, Tsutomu SASAO, "Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders" in IEICE TRANSACTIONS on Information,
vol. E88-D, no. 7, pp. 1492-1500, July 2005, doi: 10.1093/ietisy/e88-d.7.1492.
Abstract: This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EX-SOPs where some outputs of the function are minimized in the complemented form and presented techniques to minimize EX-SOPs for adders by using an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. The proposed algorithm produces solutions with a half products of AOXMIN-like algorithm in 250 times shorter time for large adders with two-valued inputs. We also proved that an n-bit adder with two-valued inputs requires at most 3
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.7.1492/_p
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@ARTICLE{e88-d_7_1492,
author={Debatosh DEBNATH, Tsutomu SASAO, },
journal={IEICE TRANSACTIONS on Information},
title={Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders},
year={2005},
volume={E88-D},
number={7},
pages={1492-1500},
abstract={This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EX-SOPs where some outputs of the function are minimized in the complemented form and presented techniques to minimize EX-SOPs for adders by using an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. The proposed algorithm produces solutions with a half products of AOXMIN-like algorithm in 250 times shorter time for large adders with two-valued inputs. We also proved that an n-bit adder with two-valued inputs requires at most 3
keywords={},
doi={10.1093/ietisy/e88-d.7.1492},
ISSN={},
month={July},}
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TY - JOUR
TI - Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders
T2 - IEICE TRANSACTIONS on Information
SP - 1492
EP - 1500
AU - Debatosh DEBNATH
AU - Tsutomu SASAO
PY - 2005
DO - 10.1093/ietisy/e88-d.7.1492
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2005
AB - This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-of-products expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EX-SOPs where some outputs of the function are minimized in the complemented form and presented techniques to minimize EX-SOPs for adders by using an extension of Dubrova-Miller-Muzio's AOXMIN algorithm. The proposed algorithm produces solutions with a half products of AOXMIN-like algorithm in 250 times shorter time for large adders with two-valued inputs. We also proved that an n-bit adder with two-valued inputs requires at most 3
ER -
English
