IEICE TRANSACTIONS on Information
Noise Metrics in Flip-Flop Designs
Summary :
About 20-45% of the total power in any VLSI circuit is consumed by the clocking system and 90% of this power consumption is spent by flip-flops. Wider datapaths, deeper pipelines, and increasing number of registers in modern processors have underscored the importance of the flip-flops. As a result, the flip-flops' performance metrics such as, power, delay, and power delay product will become a crucial factor in overall performance of processors. As technology is moving into deep submicron level, noise immunity and noise generated by any component in a digital device is also becoming a vital factor in circuit design. This paper studies various flip-flop designs for their noise immunity and noise generation metrics. It categorizes the flip-flops and reports extensive simulation results for best representative examples including the newly proposed one from the group (a patent is filed for this flip-flop). It compares power, delay, power delay product, number of transistors, number of clocked transistors, noise immunity, and noise generation for flip-flops that are reported as ones with the best performances in the literature.
- Publication
- IEICE TRANSACTIONS on Information Vol.E88-D No.7 pp.1501-1505
- Publication Date
- 2005/07/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietisy/e88-d.7.1501
- Type of Manuscript
- Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
- Category
- Digital Circuits and Computer Arithmetic
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Mohammed A. ELGAMEL, Md Ibrahim FAISAL, Magdy A. BAYOUMI, "Noise Metrics in Flip-Flop Designs" in IEICE TRANSACTIONS on Information,
vol. E88-D, no. 7, pp. 1501-1505, July 2005, doi: 10.1093/ietisy/e88-d.7.1501.
Abstract: About 20-45% of the total power in any VLSI circuit is consumed by the clocking system and 90% of this power consumption is spent by flip-flops. Wider datapaths, deeper pipelines, and increasing number of registers in modern processors have underscored the importance of the flip-flops. As a result, the flip-flops' performance metrics such as, power, delay, and power delay product will become a crucial factor in overall performance of processors. As technology is moving into deep submicron level, noise immunity and noise generated by any component in a digital device is also becoming a vital factor in circuit design. This paper studies various flip-flop designs for their noise immunity and noise generation metrics. It categorizes the flip-flops and reports extensive simulation results for best representative examples including the newly proposed one from the group (a patent is filed for this flip-flop). It compares power, delay, power delay product, number of transistors, number of clocked transistors, noise immunity, and noise generation for flip-flops that are reported as ones with the best performances in the literature.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.7.1501/_p
Copy
@ARTICLE{e88-d_7_1501,
author={Mohammed A. ELGAMEL, Md Ibrahim FAISAL, Magdy A. BAYOUMI, },
journal={IEICE TRANSACTIONS on Information},
title={Noise Metrics in Flip-Flop Designs},
year={2005},
volume={E88-D},
number={7},
pages={1501-1505},
abstract={About 20-45% of the total power in any VLSI circuit is consumed by the clocking system and 90% of this power consumption is spent by flip-flops. Wider datapaths, deeper pipelines, and increasing number of registers in modern processors have underscored the importance of the flip-flops. As a result, the flip-flops' performance metrics such as, power, delay, and power delay product will become a crucial factor in overall performance of processors. As technology is moving into deep submicron level, noise immunity and noise generated by any component in a digital device is also becoming a vital factor in circuit design. This paper studies various flip-flop designs for their noise immunity and noise generation metrics. It categorizes the flip-flops and reports extensive simulation results for best representative examples including the newly proposed one from the group (a patent is filed for this flip-flop). It compares power, delay, power delay product, number of transistors, number of clocked transistors, noise immunity, and noise generation for flip-flops that are reported as ones with the best performances in the literature.},
keywords={},
doi={10.1093/ietisy/e88-d.7.1501},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - Noise Metrics in Flip-Flop Designs
T2 - IEICE TRANSACTIONS on Information
SP - 1501
EP - 1505
AU - Mohammed A. ELGAMEL
AU - Md Ibrahim FAISAL
AU - Magdy A. BAYOUMI
PY - 2005
DO - 10.1093/ietisy/e88-d.7.1501
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2005
AB - About 20-45% of the total power in any VLSI circuit is consumed by the clocking system and 90% of this power consumption is spent by flip-flops. Wider datapaths, deeper pipelines, and increasing number of registers in modern processors have underscored the importance of the flip-flops. As a result, the flip-flops' performance metrics such as, power, delay, and power delay product will become a crucial factor in overall performance of processors. As technology is moving into deep submicron level, noise immunity and noise generated by any component in a digital device is also becoming a vital factor in circuit design. This paper studies various flip-flop designs for their noise immunity and noise generation metrics. It categorizes the flip-flops and reports extensive simulation results for best representative examples including the newly proposed one from the group (a patent is filed for this flip-flop). It compares power, delay, power delay product, number of transistors, number of clocked transistors, noise immunity, and noise generation for flip-flops that are reported as ones with the best performances in the literature.
ER -
English
