Concurrent Symbol Processing Capable VLSI Architecture for Bit Plane Coder of JPEG2000
Summary :
JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is restricted due to the high hardware cost involved in its implementation. Bit Plane Coder (BPC) is the main resource intensive component of JPEG2000. Its throughput plays a key role in deciding the overall throughput of a JPEG2000 encoder. In this paper we present the algorithm and parallel pipelined VLSI architecture for BPC which processes a complete stripe-column concurrently during every pass. The hardware requirements and the critical path delay of the proposed technique are compared with the existing solutions. The experimental results show that the proposed architecture has 2.6 times greater throughput than existing architectures, with a comparatively small increase in hardware cost.
- Publication
- IEICE TRANSACTIONS on Information Vol.E88-D No.8 pp.1878-1884
- Publication Date
- 2005/08/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietisy/e88-d.8.1878
- Type of Manuscript
- Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 2)
- Category
- Image Processing and Multimedia Systems
Authors
Keyword
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Amit Kumar GUPTA, Saeid NOOSHABADI, David TAUBMAN, "Concurrent Symbol Processing Capable VLSI Architecture for Bit Plane Coder of JPEG2000" in IEICE TRANSACTIONS on Information,
vol. E88-D, no. 8, pp. 1878-1884, August 2005, doi: 10.1093/ietisy/e88-d.8.1878.
Abstract: JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is restricted due to the high hardware cost involved in its implementation. Bit Plane Coder (BPC) is the main resource intensive component of JPEG2000. Its throughput plays a key role in deciding the overall throughput of a JPEG2000 encoder. In this paper we present the algorithm and parallel pipelined VLSI architecture for BPC which processes a complete stripe-column concurrently during every pass. The hardware requirements and the critical path delay of the proposed technique are compared with the existing solutions. The experimental results show that the proposed architecture has 2.6 times greater throughput than existing architectures, with a comparatively small increase in hardware cost.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e88-d.8.1878/_p
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@ARTICLE{e88-d_8_1878,
author={Amit Kumar GUPTA, Saeid NOOSHABADI, David TAUBMAN, },
journal={IEICE TRANSACTIONS on Information},
title={Concurrent Symbol Processing Capable VLSI Architecture for Bit Plane Coder of JPEG2000},
year={2005},
volume={E88-D},
number={8},
pages={1878-1884},
abstract={JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is restricted due to the high hardware cost involved in its implementation. Bit Plane Coder (BPC) is the main resource intensive component of JPEG2000. Its throughput plays a key role in deciding the overall throughput of a JPEG2000 encoder. In this paper we present the algorithm and parallel pipelined VLSI architecture for BPC which processes a complete stripe-column concurrently during every pass. The hardware requirements and the critical path delay of the proposed technique are compared with the existing solutions. The experimental results show that the proposed architecture has 2.6 times greater throughput than existing architectures, with a comparatively small increase in hardware cost.},
keywords={},
doi={10.1093/ietisy/e88-d.8.1878},
ISSN={},
month={August},}
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TY - JOUR
TI - Concurrent Symbol Processing Capable VLSI Architecture for Bit Plane Coder of JPEG2000
T2 - IEICE TRANSACTIONS on Information
SP - 1878
EP - 1884
AU - Amit Kumar GUPTA
AU - Saeid NOOSHABADI
AU - David TAUBMAN
PY - 2005
DO - 10.1093/ietisy/e88-d.8.1878
JO - IEICE TRANSACTIONS on Information
SN -
VL - E88-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2005
AB - JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is restricted due to the high hardware cost involved in its implementation. Bit Plane Coder (BPC) is the main resource intensive component of JPEG2000. Its throughput plays a key role in deciding the overall throughput of a JPEG2000 encoder. In this paper we present the algorithm and parallel pipelined VLSI architecture for BPC which processes a complete stripe-column concurrently during every pass. The hardware requirements and the critical path delay of the proposed technique are compared with the existing solutions. The experimental results show that the proposed architecture has 2.6 times greater throughput than existing architectures, with a comparatively small increase in hardware cost.
ER -
English
