Extracting frequently executed (hot) portions of the application and executing their corresponding data flow graph (DFG) on the hardware accelerator brings about more speedup and energy saving for embedded systems comprising a base processor integrated with a tightly coupled accelerator. Extending DFGs to support control instructions and using Control DFGs (CDFGs) instead of DFGs results in more coverage of application code portion are being accelerated hence, more speedup and energy saving. In this paper, motivations for extending DFGs to CDFGs and handling control instructions are introduced. In addition, basic requirements for an accelerator with conditional execution support are proposed. Then, two algorithms are presented for temporal partitioning of CDFGs considering the target accelerator architectural constraints. To demonstrate effectiveness of the proposed ideas, they are applied to the accelerator of a reconfigurable processor called AMBER. Experimental results approve the remarkable effectiveness of covering control instructions and using CDFGs versus DFGs in the aspects of performance and energy reduction.
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Farhad MEHDIPOUR, Hamid NOORI, Morteza SAHEB ZAMANI, Koji INOUE, Kazuaki MURAKAMI, "Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs" in IEICE TRANSACTIONS on Information,
vol. E90-D, no. 12, pp. 1956-1966, December 2007, doi: 10.1093/ietisy/e90-d.12.1956.
Abstract: Extracting frequently executed (hot) portions of the application and executing their corresponding data flow graph (DFG) on the hardware accelerator brings about more speedup and energy saving for embedded systems comprising a base processor integrated with a tightly coupled accelerator. Extending DFGs to support control instructions and using Control DFGs (CDFGs) instead of DFGs results in more coverage of application code portion are being accelerated hence, more speedup and energy saving. In this paper, motivations for extending DFGs to CDFGs and handling control instructions are introduced. In addition, basic requirements for an accelerator with conditional execution support are proposed. Then, two algorithms are presented for temporal partitioning of CDFGs considering the target accelerator architectural constraints. To demonstrate effectiveness of the proposed ideas, they are applied to the accelerator of a reconfigurable processor called AMBER. Experimental results approve the remarkable effectiveness of covering control instructions and using CDFGs versus DFGs in the aspects of performance and energy reduction.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e90-d.12.1956/_p
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@ARTICLE{e90-d_12_1956,
author={Farhad MEHDIPOUR, Hamid NOORI, Morteza SAHEB ZAMANI, Koji INOUE, Kazuaki MURAKAMI, },
journal={IEICE TRANSACTIONS on Information},
title={Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs},
year={2007},
volume={E90-D},
number={12},
pages={1956-1966},
abstract={Extracting frequently executed (hot) portions of the application and executing their corresponding data flow graph (DFG) on the hardware accelerator brings about more speedup and energy saving for embedded systems comprising a base processor integrated with a tightly coupled accelerator. Extending DFGs to support control instructions and using Control DFGs (CDFGs) instead of DFGs results in more coverage of application code portion are being accelerated hence, more speedup and energy saving. In this paper, motivations for extending DFGs to CDFGs and handling control instructions are introduced. In addition, basic requirements for an accelerator with conditional execution support are proposed. Then, two algorithms are presented for temporal partitioning of CDFGs considering the target accelerator architectural constraints. To demonstrate effectiveness of the proposed ideas, they are applied to the accelerator of a reconfigurable processor called AMBER. Experimental results approve the remarkable effectiveness of covering control instructions and using CDFGs versus DFGs in the aspects of performance and energy reduction.},
keywords={},
doi={10.1093/ietisy/e90-d.12.1956},
ISSN={1745-1361},
month={December},}
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TY - JOUR
TI - Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs
T2 - IEICE TRANSACTIONS on Information
SP - 1956
EP - 1966
AU - Farhad MEHDIPOUR
AU - Hamid NOORI
AU - Morteza SAHEB ZAMANI
AU - Koji INOUE
AU - Kazuaki MURAKAMI
PY - 2007
DO - 10.1093/ietisy/e90-d.12.1956
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E90-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2007
AB - Extracting frequently executed (hot) portions of the application and executing their corresponding data flow graph (DFG) on the hardware accelerator brings about more speedup and energy saving for embedded systems comprising a base processor integrated with a tightly coupled accelerator. Extending DFGs to support control instructions and using Control DFGs (CDFGs) instead of DFGs results in more coverage of application code portion are being accelerated hence, more speedup and energy saving. In this paper, motivations for extending DFGs to CDFGs and handling control instructions are introduced. In addition, basic requirements for an accelerator with conditional execution support are proposed. Then, two algorithms are presented for temporal partitioning of CDFGs considering the target accelerator architectural constraints. To demonstrate effectiveness of the proposed ideas, they are applied to the accelerator of a reconfigurable processor called AMBER. Experimental results approve the remarkable effectiveness of covering control instructions and using CDFGs versus DFGs in the aspects of performance and energy reduction.
ER -