IEICE TRANSACTIONS on Information
Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures
Summary :
In these days, many dynamically reconfigurable architectures have been introduced to fill the gap between ASICs and software-programmed processors such as GPPs and DSPs. These reconfigurable architectures have shown to achieve higher performance compared to software-programmed processors. However, reconfigurable architectures suffer from a significant reconfiguration overhead and a speedup limitation. By reducing the reconfiguration overhead, the overall performance of reconfigurable architectures can be improved. Therefore, we will describe temporal partitioning, which are able to amortize the reconfiguration overhead at synthesis phase or compilation time. Our temporal partitioning methodology splits a configuration context into temporal partitions to amortize reconfiguration overhead. And then, we will present benchmark results to demonstrate the effectiveness of our methodology.
- Publication
- IEICE TRANSACTIONS on Information Vol.E90-D No.12 pp.1977-1985
- Publication Date
- 2007/12/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e90-d.12.1977
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Reconfigurable Device and Design Tools
Authors
Keyword
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Jinhwan KIM, Jeonghun CHO, Tag Gon KIM, "Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures" in IEICE TRANSACTIONS on Information,
vol. E90-D, no. 12, pp. 1977-1985, December 2007, doi: 10.1093/ietisy/e90-d.12.1977.
Abstract: In these days, many dynamically reconfigurable architectures have been introduced to fill the gap between ASICs and software-programmed processors such as GPPs and DSPs. These reconfigurable architectures have shown to achieve higher performance compared to software-programmed processors. However, reconfigurable architectures suffer from a significant reconfiguration overhead and a speedup limitation. By reducing the reconfiguration overhead, the overall performance of reconfigurable architectures can be improved. Therefore, we will describe temporal partitioning, which are able to amortize the reconfiguration overhead at synthesis phase or compilation time. Our temporal partitioning methodology splits a configuration context into temporal partitions to amortize reconfiguration overhead. And then, we will present benchmark results to demonstrate the effectiveness of our methodology.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e90-d.12.1977/_p
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@ARTICLE{e90-d_12_1977,
author={Jinhwan KIM, Jeonghun CHO, Tag Gon KIM, },
journal={IEICE TRANSACTIONS on Information},
title={Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures},
year={2007},
volume={E90-D},
number={12},
pages={1977-1985},
abstract={In these days, many dynamically reconfigurable architectures have been introduced to fill the gap between ASICs and software-programmed processors such as GPPs and DSPs. These reconfigurable architectures have shown to achieve higher performance compared to software-programmed processors. However, reconfigurable architectures suffer from a significant reconfiguration overhead and a speedup limitation. By reducing the reconfiguration overhead, the overall performance of reconfigurable architectures can be improved. Therefore, we will describe temporal partitioning, which are able to amortize the reconfiguration overhead at synthesis phase or compilation time. Our temporal partitioning methodology splits a configuration context into temporal partitions to amortize reconfiguration overhead. And then, we will present benchmark results to demonstrate the effectiveness of our methodology.},
keywords={},
doi={10.1093/ietisy/e90-d.12.1977},
ISSN={1745-1361},
month={December},}
Copy
TY - JOUR
TI - Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures
T2 - IEICE TRANSACTIONS on Information
SP - 1977
EP - 1985
AU - Jinhwan KIM
AU - Jeonghun CHO
AU - Tag Gon KIM
PY - 2007
DO - 10.1093/ietisy/e90-d.12.1977
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E90-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2007
AB - In these days, many dynamically reconfigurable architectures have been introduced to fill the gap between ASICs and software-programmed processors such as GPPs and DSPs. These reconfigurable architectures have shown to achieve higher performance compared to software-programmed processors. However, reconfigurable architectures suffer from a significant reconfiguration overhead and a speedup limitation. By reducing the reconfiguration overhead, the overall performance of reconfigurable architectures can be improved. Therefore, we will describe temporal partitioning, which are able to amortize the reconfiguration overhead at synthesis phase or compilation time. Our temporal partitioning methodology splits a configuration context into temporal partitions to amortize reconfiguration overhead. And then, we will present benchmark results to demonstrate the effectiveness of our methodology.
ER -
English
