A Systolic FPGA Architecture of Two-Level Dynamic Programming for Connected Speech Recognition
Summary :
In this paper, we present an efficient architecture for connected word recognition that can be implemented with field programmable gate array (FPGA). The architecture consists of newly derived two-level dynamic programming (TLDP) that use only bit addition and shift operations. The advantages of this architecture are the spatial efficiency to accommodate more words with limited space and the absence of multiplications to increase computational speed by reducing propagation delays. The architecture is highly regular, consisting of identical and simple processing elements with only nearest-neighbor communication, and external communication occurs with the end processing elements. In order to verify the proposed architecture, we have also designed and implemented it, prototyping with Xilinx FPGAs running at 33 MHz.
- Publication
- IEICE TRANSACTIONS on Information Vol.E90-D No.2 pp.562-568
- Publication Date
- 2007/02/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e90-d.2.562
- Type of Manuscript
- PAPER
- Category
- Speech and Hearing
Authors
Keyword
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Yong KIM, Hong JEONG, "A Systolic FPGA Architecture of Two-Level Dynamic Programming for Connected Speech Recognition" in IEICE TRANSACTIONS on Information,
vol. E90-D, no. 2, pp. 562-568, February 2007, doi: 10.1093/ietisy/e90-d.2.562.
Abstract: In this paper, we present an efficient architecture for connected word recognition that can be implemented with field programmable gate array (FPGA). The architecture consists of newly derived two-level dynamic programming (TLDP) that use only bit addition and shift operations. The advantages of this architecture are the spatial efficiency to accommodate more words with limited space and the absence of multiplications to increase computational speed by reducing propagation delays. The architecture is highly regular, consisting of identical and simple processing elements with only nearest-neighbor communication, and external communication occurs with the end processing elements. In order to verify the proposed architecture, we have also designed and implemented it, prototyping with Xilinx FPGAs running at 33 MHz.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e90-d.2.562/_p
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@ARTICLE{e90-d_2_562,
author={Yong KIM, Hong JEONG, },
journal={IEICE TRANSACTIONS on Information},
title={A Systolic FPGA Architecture of Two-Level Dynamic Programming for Connected Speech Recognition},
year={2007},
volume={E90-D},
number={2},
pages={562-568},
abstract={In this paper, we present an efficient architecture for connected word recognition that can be implemented with field programmable gate array (FPGA). The architecture consists of newly derived two-level dynamic programming (TLDP) that use only bit addition and shift operations. The advantages of this architecture are the spatial efficiency to accommodate more words with limited space and the absence of multiplications to increase computational speed by reducing propagation delays. The architecture is highly regular, consisting of identical and simple processing elements with only nearest-neighbor communication, and external communication occurs with the end processing elements. In order to verify the proposed architecture, we have also designed and implemented it, prototyping with Xilinx FPGAs running at 33 MHz.},
keywords={},
doi={10.1093/ietisy/e90-d.2.562},
ISSN={1745-1361},
month={February},}
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TY - JOUR
TI - A Systolic FPGA Architecture of Two-Level Dynamic Programming for Connected Speech Recognition
T2 - IEICE TRANSACTIONS on Information
SP - 562
EP - 568
AU - Yong KIM
AU - Hong JEONG
PY - 2007
DO - 10.1093/ietisy/e90-d.2.562
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E90-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2007
AB - In this paper, we present an efficient architecture for connected word recognition that can be implemented with field programmable gate array (FPGA). The architecture consists of newly derived two-level dynamic programming (TLDP) that use only bit addition and shift operations. The advantages of this architecture are the spatial efficiency to accommodate more words with limited space and the absence of multiplications to increase computational speed by reducing propagation delays. The architecture is highly regular, consisting of identical and simple processing elements with only nearest-neighbor communication, and external communication occurs with the end processing elements. In order to verify the proposed architecture, we have also designed and implemented it, prototyping with Xilinx FPGAs running at 33 MHz.
ER -
English
