IEICE TRANSACTIONS on Information
Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1)
Summary :
The moduli set (2n, 2n+1-1, 2n-1) which is free of (2n+1)-type modulus is profitable to construct a high-performance residue number system (RNS). In this paper, we derive a reduced-complexity residue-to-binary conversion algorithm for the moduli set (2n, 2n+1-1, 2n-1) by using New Chinese Remainder Theorem (CRT). The resulting converter architecture mainly consists of simple adder and multiplexer (MUX) which is suitable to realize an efficient VLSI implementation. For the various dynamic range (DR) requirements, the experimental results show that the proposed converter can significantly achieve at least 23.3% average Area-Time (AT) saving when comparing with the latest designs. Based on UMC 0.18 µm CMOS cell-based technology, the chip area for 16-bit residue-to-binary converter is 931
- Publication
- IEICE TRANSACTIONS on Information Vol.E91-D No.7 pp.2058-2060
- Publication Date
- 2008/07/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e91-d.7.2058
- Type of Manuscript
- LETTER
- Category
- Computer Systems
Authors
Keyword
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Su-Hon LIN, Ming-Hwa SHEU, Chao-Hsiang WANG, "Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1)" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 7, pp. 2058-2060, July 2008, doi: 10.1093/ietisy/e91-d.7.2058.
Abstract: The moduli set (2n, 2n+1-1, 2n-1) which is free of (2n+1)-type modulus is profitable to construct a high-performance residue number system (RNS). In this paper, we derive a reduced-complexity residue-to-binary conversion algorithm for the moduli set (2n, 2n+1-1, 2n-1) by using New Chinese Remainder Theorem (CRT). The resulting converter architecture mainly consists of simple adder and multiplexer (MUX) which is suitable to realize an efficient VLSI implementation. For the various dynamic range (DR) requirements, the experimental results show that the proposed converter can significantly achieve at least 23.3% average Area-Time (AT) saving when comparing with the latest designs. Based on UMC 0.18 µm CMOS cell-based technology, the chip area for 16-bit residue-to-binary converter is 931
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.7.2058/_p
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@ARTICLE{e91-d_7_2058,
author={Su-Hon LIN, Ming-Hwa SHEU, Chao-Hsiang WANG, },
journal={IEICE TRANSACTIONS on Information},
title={Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1)},
year={2008},
volume={E91-D},
number={7},
pages={2058-2060},
abstract={The moduli set (2n, 2n+1-1, 2n-1) which is free of (2n+1)-type modulus is profitable to construct a high-performance residue number system (RNS). In this paper, we derive a reduced-complexity residue-to-binary conversion algorithm for the moduli set (2n, 2n+1-1, 2n-1) by using New Chinese Remainder Theorem (CRT). The resulting converter architecture mainly consists of simple adder and multiplexer (MUX) which is suitable to realize an efficient VLSI implementation. For the various dynamic range (DR) requirements, the experimental results show that the proposed converter can significantly achieve at least 23.3% average Area-Time (AT) saving when comparing with the latest designs. Based on UMC 0.18 µm CMOS cell-based technology, the chip area for 16-bit residue-to-binary converter is 931
keywords={},
doi={10.1093/ietisy/e91-d.7.2058},
ISSN={1745-1361},
month={July},}
Copy
TY - JOUR
TI - Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1)
T2 - IEICE TRANSACTIONS on Information
SP - 2058
EP - 2060
AU - Su-Hon LIN
AU - Ming-Hwa SHEU
AU - Chao-Hsiang WANG
PY - 2008
DO - 10.1093/ietisy/e91-d.7.2058
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 7
JA - IEICE TRANSACTIONS on Information
Y1 - July 2008
AB - The moduli set (2n, 2n+1-1, 2n-1) which is free of (2n+1)-type modulus is profitable to construct a high-performance residue number system (RNS). In this paper, we derive a reduced-complexity residue-to-binary conversion algorithm for the moduli set (2n, 2n+1-1, 2n-1) by using New Chinese Remainder Theorem (CRT). The resulting converter architecture mainly consists of simple adder and multiplexer (MUX) which is suitable to realize an efficient VLSI implementation. For the various dynamic range (DR) requirements, the experimental results show that the proposed converter can significantly achieve at least 23.3% average Area-Time (AT) saving when comparing with the latest designs. Based on UMC 0.18 µm CMOS cell-based technology, the chip area for 16-bit residue-to-binary converter is 931
ER -
English
