IEICE TRANSACTIONS on Information
A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors
Summary :
The multi-process execution in dynamically reconfigurable processors is a technique to enhance throughput by trying to exploit more inherent parallelism of applications. Basically, a total process for an application is divided into small processes, assigned into limited areas of a reconfigurable array, and concurrently executed in a pipelined manner. In order to improve the efficiency of the multi-process execution, a systematic method for mapping processes onto a reconfigurable array consisting of multiple hardware execution units is essential. This paper proposes and investigates a systematic method for mapping an application modeled as a Kahn Process Network onto a dynamically reconfigurable processing array. In order to execute streaming applications in a pipelined manner, the size of Tiles, which is a unit area of dynamically reconfigurable array, and the grouping of processes are adjusted. Using real applications such as DCT, JPEG encoder and Turbo encoder, the impact of different versions mapped onto the NEC Dynamically Reconfigurable Processor on performance is evaluated. Evaluation results show that our proposed mapping algorithm achieves the best performance in terms of the throughput and the execution time.
- Publication
- IEICE TRANSACTIONS on Information Vol.E91-D No.9 pp.2312-2322
- Publication Date
- 2008/09/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e91-d.9.2312
- Type of Manuscript
- PAPER
- Category
- Computer Systems
Authors
Keyword
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Vu MANH TUAN, Hideharu AMANO, "A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors" in IEICE TRANSACTIONS on Information,
vol. E91-D, no. 9, pp. 2312-2322, September 2008, doi: 10.1093/ietisy/e91-d.9.2312.
Abstract: The multi-process execution in dynamically reconfigurable processors is a technique to enhance throughput by trying to exploit more inherent parallelism of applications. Basically, a total process for an application is divided into small processes, assigned into limited areas of a reconfigurable array, and concurrently executed in a pipelined manner. In order to improve the efficiency of the multi-process execution, a systematic method for mapping processes onto a reconfigurable array consisting of multiple hardware execution units is essential. This paper proposes and investigates a systematic method for mapping an application modeled as a Kahn Process Network onto a dynamically reconfigurable processing array. In order to execute streaming applications in a pipelined manner, the size of Tiles, which is a unit area of dynamically reconfigurable array, and the grouping of processes are adjusted. Using real applications such as DCT, JPEG encoder and Turbo encoder, the impact of different versions mapped onto the NEC Dynamically Reconfigurable Processor on performance is evaluated. Evaluation results show that our proposed mapping algorithm achieves the best performance in terms of the throughput and the execution time.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e91-d.9.2312/_p
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@ARTICLE{e91-d_9_2312,
author={Vu MANH TUAN, Hideharu AMANO, },
journal={IEICE TRANSACTIONS on Information},
title={A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors},
year={2008},
volume={E91-D},
number={9},
pages={2312-2322},
abstract={The multi-process execution in dynamically reconfigurable processors is a technique to enhance throughput by trying to exploit more inherent parallelism of applications. Basically, a total process for an application is divided into small processes, assigned into limited areas of a reconfigurable array, and concurrently executed in a pipelined manner. In order to improve the efficiency of the multi-process execution, a systematic method for mapping processes onto a reconfigurable array consisting of multiple hardware execution units is essential. This paper proposes and investigates a systematic method for mapping an application modeled as a Kahn Process Network onto a dynamically reconfigurable processing array. In order to execute streaming applications in a pipelined manner, the size of Tiles, which is a unit area of dynamically reconfigurable array, and the grouping of processes are adjusted. Using real applications such as DCT, JPEG encoder and Turbo encoder, the impact of different versions mapped onto the NEC Dynamically Reconfigurable Processor on performance is evaluated. Evaluation results show that our proposed mapping algorithm achieves the best performance in terms of the throughput and the execution time.},
keywords={},
doi={10.1093/ietisy/e91-d.9.2312},
ISSN={1745-1361},
month={September},}
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TY - JOUR
TI - A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors
T2 - IEICE TRANSACTIONS on Information
SP - 2312
EP - 2322
AU - Vu MANH TUAN
AU - Hideharu AMANO
PY - 2008
DO - 10.1093/ietisy/e91-d.9.2312
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E91-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2008
AB - The multi-process execution in dynamically reconfigurable processors is a technique to enhance throughput by trying to exploit more inherent parallelism of applications. Basically, a total process for an application is divided into small processes, assigned into limited areas of a reconfigurable array, and concurrently executed in a pipelined manner. In order to improve the efficiency of the multi-process execution, a systematic method for mapping processes onto a reconfigurable array consisting of multiple hardware execution units is essential. This paper proposes and investigates a systematic method for mapping an application modeled as a Kahn Process Network onto a dynamically reconfigurable processing array. In order to execute streaming applications in a pipelined manner, the size of Tiles, which is a unit area of dynamically reconfigurable array, and the grouping of processes are adjusted. Using real applications such as DCT, JPEG encoder and Turbo encoder, the impact of different versions mapped onto the NEC Dynamically Reconfigurable Processor on performance is evaluated. Evaluation results show that our proposed mapping algorithm achieves the best performance in terms of the throughput and the execution time.
ER -
English
